STM32 MCUs products

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Resolved! STM32F405 - Backup SRAM not preserved

I have a STM32F405 with a coin cell on VBAT and I haven't been able to get the Backup SRAM or RTC to preserve contents when removing main power.  The same code works fine on another board that has a STM32F407. //Works on STM32F407 - Fails on STM32F40...

Resolved! Nucleo-144 STM32H755ZI vs STM32F767ZI

Hey there,I am facing a problem with the clocks on the STM32H755ZI. When I let a timer run at 50 kHz I get only smt. like 49.92 kHz out of it with sigma = 13 Hz. So there is at any frequency a steady offset of -1.2% and a sigma deviation of 0.03%. I ...

lserrnt_0-1694156704155.png lserrnt_1-1694156832487.png lserrnt_2-1694156898240.png
lserrnt by Associate II
  • 10 replies
  • 0 kudos

Resolved! Clock enable for SWD ports (STM32G0)

I'm a bit confused about the necessity of clocking the SWD ports using STM32G0B1 chip.There is a I/O port clock enable register (RCC_IOPENR) that enables the functioning of each of the GPIO ports (Port A - Port F), its reset state is all zeroes, so n...

AYash.1 by Associate II
  • 4 replies
  • 1 kudos

Resolved! STM32 clock switching, systick

Hello, I have a simple question: What is the way to update the SysTick configuration after changing the clocks at runtime? I am switching SYSCLK between two modes:1) RUN mode: HSE 32 MHZ2) LPRUN mode: MSI 2 MHZAfter changing to (2), the HAL_GetTick()...

MHast.1 by Associate II
  • 1 replies
  • 0 kudos

Debugging dual core Bootloader on STM32H7

I'm trying to develop a bootloader for a dual core STM32H7, running on the CM7. I'm starting by trying to modify my user project for it.I've moved the user code up a bank:FLASH   (rx)   : ORIGIN = 0x08020000, LENGTH = 896K and put in a IVT offset on ...

Resolved! PLL clock division in STM32H7 for fadc_ker_ck

Hi,a footnote(4) in STM32H7 reference manual RM0468 Table 56 regarding the maximum allowed frequency for ADC says"With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even".Does this recommendation apply to the actual DIVXx regist...