Hi all, I have already searched on the forms and in general did not find an answer to my problem, I will be very grateful to you for help.I need to create an output signal with a frequency of 100 Mhz as CLK in STM32H745. I used the Discovery Boards ...
Hello,STM32F103RB microcontroller.The Figure1 (see attached image) shows clock tree of STM32F103RB microcontroller. Before TIM6CLK, there is a block, which is highlighted in red rectangle. What's IF (APB1 PRESCALER = 1) x1 ELSE x2 label in this red ...
Hello. I have a STM32H747XI project. This MCU has both CM4 and CM7 cores. I can reset both of them, when I use NVIC_SystemReset() function. How can I reset only CM7 core from CM4 core?
Hi,I am having uart baudrate problems while HSI clock as uart source clock. No problem with PCLK as source with the same uart. In Cube IDE (V1.16.0) and F7 software package (V.17.2), I get different values for HSI_CALIBRATION:Ide gets as 0x10 while r...
I used STM32F446VET7 on the board I PCB printed. When I use HSI, I can debug without any problem, but when I want to use HSE, SystemClock_Config(); function enters ErrorHandler().Can you help me?
Hello,I sort of feel *** not to get sure there not a best solution. I develop an Audio board, with USB HS. I will have a good 49.152MHz clock to drive the SAI, and I wanted to ue it for the HSE.49.152 * 125 / 256 = 24MHz that I need for the ULPI. Loo...
Hi ST Community,Does anyone know how the HSICAL48 value gets loaded into RCC_CRRCR? The RM says "These bits are initialized at startup with the factory-programmed HSI48 calibration trim value", so I assume the trim value is stored somewhere in system...
Hi,If I configure the LSI as clock source my STM32C011F4U6TR code stuck at this pointHowever there is no problem if I configure HSISYS as clock source.Why? Could anyone help me with this issue?Thanks in advance,Gaston
I am trying to change the system clock on my STM32F410RB using register programming. I have setup an SPI protocol to an external DAC IC which needs a minimum of 100ns (10MHz) clock period. The SPI allows for a maximum of 8MHz (fPCLK/2) at default clo...
