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Resolved! STM32U5A5: DCache as "memory"?

My question might sound "strange" for HW experts.My STM32U5A5 MCU has DCache (16KByte). Datasheet says: used when external memory is connected (e.g. NAND/NOR flash, OCTOSPI).DCache is not used for internal memory (when running from MCU flash or inter...

tjaekel by Senior
  • 3 replies
  • 3 kudos

STM32H7 M7 to Update M4 flash area

Hello community! I am developing an app that is running in an H7 MCU, the M7 core app is "turning on" the M4 and then is running to an external flash where is the actual M7 code.I am looking to implement an update in this M7 "bootloader". As i unders...

urbito by Associate III
  • 5 replies
  • 0 kudos

STM32Uxx: OCTALSPI direction signal (is missing)

I need level shifters, using QSPI signals with 1V2 logic (MCU can just be set for 1V8, so I need level shifters).I have realized: bi-directional level shifters for 1V2 are pretty slow (and rare). Level shifters which have a DIR signal (to turn the di...

tjaekel by Senior
  • 1 replies
  • 1 kudos

STM32 Technical Updates are back : 2024 Newsletter 1 !

Dear STM32 users and developers, This new thread is back and is dedicated for our technical developers community to share last STM32 updates, the first part will be products documentation news such as datasheets, Erratas, Applications notes  followed...

STM32 Technical updates - 2024 Newsletter1.png
STOne-32 by ST Employee
  • 4 replies
  • 13 kudos

Resolved! STM32U5xx: SPI3 slave fails at 80 MHz

I use OCTOSPI as SPI master and listen via SPI3 as Slave (in SW NCS mode) what was sent from master.SPI3 Slave fails for clock speed 80 MHz (larger as 54 MHz:(Symptoms:the data bytes on SPI3 slave are wrong (they look like shifted by one bit)running ...

tjaekel by Senior
  • 3 replies
  • 1 kudos