About SZano

SZano · 2024-07-04

I'd like an opinion on this issue with timers; I have working code, but it took me a while to understand that the code was actually working (though not while debugging).I'm using STM32F446RT.I'm configuring two timers so that one timer is a master, a...

SZano · 2024-06-27

I'm using STM32F446.I'm generating PWM signals using TIM1 and TIM8 (on APB2, which runs at 90MHz, and 180MHz for the timers).I'm also generating PWM signals using TIM4 and TIM12 (on APB1, which runs at 45MHz, and 90MHz for the timers).I start each PW...

SZano · 2023-09-20

In the STM32L562 reference manual (RM0438), v7.0, the section 11.6.13 "GPIO register map" is missing the registers MODER and PUPDR (which are documented in the preceding sections).

SZano · 2023-07-28

With STM32L562, I'm implementing a firmware update strategy using the double flash bank.I write the new firmware in the second bank, then toggle the FLASH_OPTR_SWAP_BANK option bit, and then trigger a reset with OBL_LAUNCH.To write to the second bank...

SZano · 2021-11-08

The datasheet (DS10685 Rev 6) in Table 16 says that the VLCD pins are:PB0/LCD_VLCD3PB2/LCD_VLCD2PE11/LCD_VLCD1PE12/LCD_VLCD3PB12/LCD_VLCD1In the reference manual RM0367 Rev 7 (for STM32L0x3)Section 10.2.2 (SYSCFG_CFGR2), for bits LCD_CAPA:Bit 1 contr...

SZano · 2024-07-09

Thanks for the information.However, I still have doubts.From my tests, everything works (even when single-stepping) as long as I don't freeze TIM9. So, it seems the issue is not related to halting the CPU. Also, I would expect the CPU to be halted, b...

SZano · 2024-06-27

>> The prescaler within the TIM is NOT VISIBLE, you can set the COUNT, your can't see the COUNTER.Now I see what you mean.Yes, the prescaler is a counter itself, which is not accessible, and its overflow signal is what actually feeds the timer counte...

SZano · 2024-06-27

Could you please elaborate? I tried this:HCLK 180MHzAPB1_timer = HCLK / 4 * 2 = 90MHzAPB2_timer = HCLK / 2 * 2 = 180MHz And also this:HCLK 180MHzAPB1_timer = HCLK / 4 * 2 = 90MHzAPB2_timer = HCLK / 4 * 2 = 90MHz Both use the APB prescaler, not the pr...

SZano · 2024-06-27

I start them once and leave them freely running.I don't have a minimal example now, I'll prepare one tomorrow.

SZano · 2021-11-15

Thank you.Given the mistake in the eval schematic, the silkscreen is wrong too. I guess this is impractical to fix, though.

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TIM trigger is skipped while single-stepping with frozen TIM

APB1 and APB2 are out of sync

Missing info in reference manual

SWAP_BANK, OB launch, and spurious resets

[L0] LCD VLCD: wrong documentation and code generation

Re: TIM trigger is skipped while single-stepping with frozen TIM

Re: APB1 and APB2 are out of sync

Re: APB1 and APB2 are out of sync

Re: APB1 and APB2 are out of sync

Re: [L0] LCD VLCD: wrong documentation and code generation