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Resolved! Possible to route ETR to a TIM1 channel

I have a product using a STM32H745ZIT that has an input signal connected to TIM1 ETR and in the normal case, an edge on the ETR using slave mode trigger results in a one pulse pwm output a set time later driven on TIM1 CH1 and TIM1 CH2.  A new use ca...

GHolc.1 by Associate III
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DFSDM sinc filter STM32H743 Problem

Hello,I am trying to use the DFSDM module on the Nucleo-H743ZI2 board .As a minimal example, i tried to use a sinc filter of 2. order with a FOSR of 4.Channel0 is activated in the parallel mode, standard data packing mode and the setting to take data...

set3.PNG set0.PNG set1.PNG set4.PNG
Uloff.4 by Associate II
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Flash wait states meaning

Hi i have a generic doubt about falsh wait states:Say we configured the PLL to run system core clock at 160 M Hz, with flash wait states as 5.Then is cpu is equvilent to 32 MHZ core performance? (assuming 1 clk/ 1 inst, no ART's)Could some one help m...

RKall.1 by Associate II
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  • 2 replies
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