When installing some StellarStudio plugins http://*.srxstudio.org , you can meet the issue : sun.security.validator.ValidatorException: PKIX path building failed It is typical IT Issue :face_screaming_in_fear: in each corporate company. “"Path bui...
Dear all, We are thrilled to announce that as of today, March 1st, 2024, SR5E1 device support in StellarStudio is available to the mass market ! This means that any user can effortlessly download the official StellarStudio installation packag...
How to read ADC conversion results on the GTM/MCS.Here is my code:MCS side:AN8 = __brd(0x00005440);AN9 = __brd(0x0000544C);AN16 = __brd(0x00005480);AN17 = __brd(0x00005488);AN26 = __brd(0x000054D0);AN27 = __brd(0x000054D8);AN40 = __brd(0x00005540);...
I want to read and write data by serial connection.For test, I import samples "SPC58ECxx_RLA SERIAL Test Application for Discovery" from application library.In my understanding, the "main.c" function write "Hello World!" by serial connection.my envir...
Hello, I am Erdem.I am an R&D engineer at Devimsel Elektronik. I will use the SPC560P processor on my own PCB board. For this I need instructions for using SPC5 studio. How do I make configurations such as pin and clock tree? Can I get an instruction...
Hi,I am using:Processor: SPC58NE84C3Compiler: FreeGCCWe have a working software setup running with optimization level "O0". However, when we enable "O1", we encounter issues in certain states where it triggers the the Machine Check Interrupt (offset ...
I am using sample example from SPC58NN84E7, I could see there is common ISR function for all the modules, of course with different vector number, But i am not able to see how this #define IRQ_HANDLER(id) void id(void) function address is registered...
Hello,I have a question regarding the L9800 product (LS driver). The value of the CFG_2.FR_ADJ bit in "Table 12. Coefficient overview" differs from the value of the CFG_2.FR_ADJ bit in "Table 18. Register addressing space" in the datasheet. Could you...
I have flashed the application onto the HSM core of SR6G7, and I can see that the HSM core is not running up without a trigger from the Host core. After some analysis, I found that the HSM core requires a power mode change from DRUN mode to RUN mode ...
[Part Number] AEK-MCU-C4MLIT1, SPC58EC80E5[Environment] SPC5studio 6.0, UDE starterkit 2021.05(x86-64bit), integrated PLS debugger[demo] SPC58ECxx_RLA AI BMS Test Application for Discovery[Details]I am working on a SPC5studio demo about the AI applic...
[board]: AEK-MCU-C4MLIT1[MCU]: SPC58EC80E5I want to obtain the number of CPU cycles required for a function to execute.
Hello.I am using an MCU SPC560B50L5 in an LQFP144 package on the board, connected via JTAG. I'm trying using J-Link V11 SEGGER J-Link Registration V8.10 program.When I try to connect, I get the error: “Unable to enable OnCE 10-bit TAP controller Fai...