Hi i have a generic doubt about falsh wait states:Say we configured the PLL to run system core clock at 160 M Hz, with flash wait states as 5.Then is cpu is equvilent to 32 MHZ core performance? (assuming 1 clk/ 1 inst, no ART's)Could some one help m...

if we test with ( HAL_FLASHEx_Erase(&eraseInitStruct, &SECTORError) != HAL_OK) function there is no impact on foreground interrupts. But per design notes of dual bank concepts there should not be any hang/impact on first bank operation when we erase/...

Most of the time non predicted values coming in graph (very big numbers but actual sine values are unit vectors). My core clock is 170 Mhz,Timer1 period overflow interrupt rate is 10 K Hzintercafe SWD clock is 24000 K HzSerial wire viewer clock is 2...