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Hi all.I'm new to STM, but have been designing and making embedded MCU products for over ten years.I was drawn to the STM32F105 series because of the USB DFU, to allow for field updates for prospective customers to update a product we're developing. ...
/** * @brief DMA Linked-list yWaveQ configuration * @PAram None * @retval None */ HAL_StatusTypeDef MX_yWaveQ_Config(void) { HAL_StatusTypeDef ret = HAL_OK; /* DMA node configuration declaration */ DMA_NodeConfTypeDef pNodeConfig; ...
I am trying to implement a GPDMA driver in a C project that does not use HAL, and have been really struggling to get something working. I have read everything I can find on this peripheral, multiple times, and still don't quite understand how one wou...
I am trying to debug some functions to write to the memory mapped QSPI. When I go to debug it, I notice that before any functions even run the QPSI is in HAL_QSPI_STATE_ERROR, therefore I cannot test my code to see if is running because it is depende...
Are the steps followed for RTC calibration the same for crystal and temperature variation?How is the calibration register value selected for temperature variation?
I have selected the RTC calibration as 512Hz. Will I be able to perform RTC smooth calibration if my frequency obtained on the RTC calib pin is beyond the range 511.75Hz - 512.25Hz. How do I calibrate the RTC beyond this range ??
When trying to program the STM32L4P5RE, I get an assertion failure when trying to program the second bank like this:HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data)This call fails if my address is in the second bank `0x08080000`. Looki...
Hello, I am working with an STM32G4 microcontroller and noticed an unexpected behavior regarding Bit 20 (BFB2) in the User & Read Protection Option Bytes.According to the reference manual, BFB2 is a read-only bit.After performing an option bytes eras...
I have two Nucleo boards that are connected with a CAN bus (Transceiver SN65HVD230). I would like to communicate with standard CAN, eight data bytes, data rate 50000 bit/s. For the F407 all TX & RX events are triggering (reused old working code) the ...
I'm trying to understand how the CSR register works. I though initially that the various reset reason bits are mutually exclusive. That turns out not to be the case. For example, I'm seeing SFTRSTF and PINRSTF together, and also BORRSTF with PINRSTF....
