Resolved! problem using PLL as SYSCLK over 200MHz on H5
I am trying to increase FCLK, and I changed the voltage scaling to VOS0, and configured the PLL1 for 240 MHz (src=HSI (HSIDIV=2), M=2, N=30, P=2), but it did not boot (it freezes when a change the system clock mux to PLL1). I realized when I decrease...