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When the MCU is placed in Standby Mode, where does the CPU begin to execute when exiting the mode? (for example, on an RTC event) Is it a reset or a return from interrupt? RM0394 isn't clear on this.
Hi all, I am trying to use FDCAN with Baud rate switch (500 kB / 2 MBit) activated and I want to send 64 Byte. Processor is STM32H7A3. Project was set up with CubeMX V. 6.11.1 and HAL FW_H7 V1.11.2. Clock for FDCAN is 80 MHz. The problem is that th...
What is the difference between STM32F411VEH6U and STM32F411VEH6? What does the suffix U mean?
STM32L072 – LPTIM1 external pulse counting with LSE in STOP mode not workingDescription:Hello,I am trying to configure LPTIM1 on an STM32L072 to count external pulses from a button connected to PB5 (LPTIM1_IN1). The goal is to keep counting pulses wh...
The VENC peripheral on the N6 boasts a hardware handshake path with the DCMIPP peripheral, potentially allowing full compression of each frame to occur with very little active RAM. From what I can find, the DCMIPP capture starts, then the VENC is tol...
I have written a custom bootloader that is running on a Nucleo-L433RC-P board. The application uses USB CDC to call the bootloader and the bootloader uses USB DFU to download the application. I wanted to use USB to call the custom bootloader, rather ...
Our STM32H745XIH microcontroller enters an infinite loop after updating the software with “Release” compilation flags (optimization enabled). This only happens with a specific build, and changing a single piece of code that is definitely not related ...
I'm attempting to use a custom LCD daughter board designed to plug onto the STM32U5G9J-DK1 in place of the round display that comes with the DK1. The schematics for the DK1 have a note in read indicating that the DSI_CK_N and DSI_CK_P pins are revers...
Hi,My battery (++ LTO/Bucks) that runs everything on my PCBA is connected to VBAT (pin 1). Before the connection I have a voltage divider factor of roughly 1.374, but what I read on the pin via ADC1 channel 18 (what VBAT is routed to internally) seem...
The errata for the STM32U575 series includes the following: We would like to use the first option of the 2 listed workarounds (the one that does NOT require disabling and reenabling the ICACHE). Does ST have any implementation examples of this worka...
