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Hello ST experts,I have a weird experience with UART communication between two STM32G4 microcontrollers. MCU1 sends 10 bytes to MCU2 via UART. Both UARTS are configured with 9600 Baud rate with DMA in circular mode. The Problem arises when the MCU1 i...
Hi, everyoneI recently encountered a strange phenomenon. I opened three DMA channels on the STM32G474RBT6.The first one is Channel 1 of DMA1 (circular mode), which is used for automatically collecting the data converted by ADC.The second one is chann...
In my embedded software project, I need to write a bootloader. I wrote an application code for the bootloader and testing, and everything is fine so far, but the delay function in the application code is not working. I think the reason for this is th...
I am designing a system that will utilize the dual bank feature of the STM32 devices to make a robust system for OTA updates. I am currently using a STM32U545 for my project and have questions about writing to the FLASH_OPTR to change the SWAP_BANK b...
Hello, We are facing an intermittent CAN-FD issue in the field and would appreciate guidance from the community. Our system has two devices on the bus (no other device on the bus) using a request–response architecture. The master sends a request ever...
Hello,I have not found the maximum TRACECLK frequency of the STM32H725 in the documentation. It looks like it is generated by PLL1 with flexible division ratios and thus can attain values that are not realistic for I/Os (100 to 220 MHz for Speed 11 a...
Hello, I am reading 6.3.30 LCD-TFT controller (LTDC) section to interface with DS90C385A (LCD) or ADV7125 (VGA) Assume that LCD Clock (pixel clock) polarity is set to high. Ideally, we can expect rising edge of clock aligned to the middle of the data...
Hello, How to perform dual-core communication on STM32H747?
There is this errata for STM32G0B12.2.10 Prefetch failure when branching across flash memory banksDescriptionIn rare cases, the code prefetch may fail upon branching and function calls across flash memory banks,regardless of the DUAL_BANK and nSWAP_B...
I am using a Nucleo-N657X0-Q board to prototype a data collection system that collects samples from an ADC connected to the SAI peripheral and places the results in RAM. If I use CPU AXI RAM0 as the destination this works correctly, but if I change t...
