STM32 MCUs products

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STM32H7 Hyperram Write sequence not correct

Dear ST-community, im Niklas Diehm and currently working on a student project, developing a Formula Student racecar. This year, we want to build a new dashboard for the driver. Therefore, we want to use a STM32H725ZGT6 with an external Hyperram S70KL...

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about Execute in place using dual quad spi

What I want to do is XIP with DUAL QUAD SPI.The environment is as follows.Use Board : nucleo l4r5ziIDE : Atollic TrueSTUDIO® for STM32, Built on Eclipse Neon.1a.(Version: 9.3.0)FLASH : W25Q64JVThe connection diagram of the board and FLASH is shown be...

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Myasu.1 by Senior
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  • 9 replies
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Resolved! STM32U5A5: DCache as "memory"?

My question might sound "strange" for HW experts.My STM32U5A5 MCU has DCache (16KByte). Datasheet says: used when external memory is connected (e.g. NAND/NOR flash, OCTOSPI).DCache is not used for internal memory (when running from MCU flash or inter...

tjaekel by Senior III
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  • 3 replies
  • 3 kudos

Resolved! Data is not stored in the FIFO when FSEL is 1

What I want to do is send Write Enable instruction to external Flash and erase.The environment is as follows.Use Board : nucleo l4r5ziIDE : Atollic TrueSTUDIO® for STM32, Built on Eclipse Neon.1a.(Version: 9.3.0)FLASH : W25Q64JVThe connection diagram...

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Myasu.1 by Senior
  • 248 Views
  • 1 replies
  • 0 kudos

Resolved! STM32H735G BSP_OSPI_NOR_Erase_Chip(0) not work

I have STM32H735G configured and worked with TouchGFX,. I have tihis configuration works:MX_OCTOSPI1_Init ->okayBSP_OSPI_NOR_Init(0, &ospi_nor_int)-> okayBSP_OSPI_NOR_EnableMemoryMappedMode(0)-> okay(post code)static void MX_OCTOSPI1_Init(void){ /* U...