STM32 MCUs Products
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Resolved! STM32H7 M7 to Update M4 flash area
Hello community! I am developing an app that is running in an H7 MCU, the M7 core app is "turning on" the M4 and then is running to an external flash where is the actual M7 code.I am looking to implement an update in this M7 "bootloader". As i unders...
Question about I2C TXIS bit in stm32g071rb
Hello, I'm studing I2C on stm32g071rb and I have a question about it.In the datasheet there is this line: "In the case of a write transfer, the TXIS flag is set after each byte transmission, after the 9th SCL pulse when an ACK is received", but for t...
Resolved! ADC with DMA restart
Hello,I'm using ADC together with DMA.At first start of ADC and DMA all worked like expected.At 2nd and following starts, the first value received from DMA is always zero / invalid.Now I have found out that it works if between two DMA transfers I use...
STM32H753 FDCAN1 RX FIFO 1 concern
Hi All,I have a peculiar observation in one of our legacy codes, wherein I do not observe RX FIFO 1 callback being triggered.I observe hfdcan1.Init.ExtFiltersNbr is set to 0 and HAL_FDCAN_ConfigFilter() is NOT called. I am unaware if this is purposel...
Resolved! STM32G473 executing from FLASH while programing FLASH
Hello,I'm having an issue while programming a small section of FLASH memory during runtime of my device.Our device executes its program from FLASH memory. In-addition, we reconfigured the systick timer to run at 20kHz and this is the heartbeat of our...
Algorithm for loading into external memory MT25QL512A & STM32H7
Hi, I'm trying to write an algorithm to load into external memory in QSPI_Dual_mode MT25QL512A for KEIL. I followed this instruction. The algorithm works BUT! when the firmware exceeds 90040001H an error occurs during verification. Smaller programs a...
Resolved! [STM32H7] When I set the MPU at the address 0x30000000,Program entry HardFault
The configuration of Cubemx is as followsThe configured address is the address of SRAM1-3，given this configuration, why does "Strongly ordered memory" cause a HardFault Thanks.
Interleaved peak current control channels using slope compenstation on Nucleo-F334R8
Could someone clarify if the Nucleo-F334R8 boards can operate two interleaved channels with using peak current mode control, each channel would need its own slope compensation. I understand the board can do a single phase and has 3 DACs, but I see i...
