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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Resolved! STM32H5 - ADC DMA - Standard Request Example

HelloI am looking for an example to get the ADC regular sequence transferred by DMA to memory going.I use TIM15 to trigger the ADC regular sequence, which has four measurements, every 5 milliseconds. When I activate the EOS IRQ and toggle a GPIO I se...

IGärt.1 by Associate II
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  • 2 replies
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PWM sine gen two timers idea

Hi, req is generate sine wave and manage frequency precisely . My design require range 2Hz to 10Hz with for example step 0,002Hz.My idea is one PWM timer for sine with same table for exampel 10bit. Second linked timer for manage one sample time on PW...

MM..1 by Chief II
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Resolved! Enable/ disable EXTI interrupts using HAL

Hey guys.I need to enable/disable the line 14 of the EXTI interrupts multiple times, using HALDo i just use the HAL_NVIC_DisableIRQ  HAL_NVIC_EnableIRQ  ( and HAL_NVIC_SetPriority whenever i re-enable the line?), providing the correct handle to the a...

STM32H7 ADC Triggered by timer at high frequency.

Hello everyone.I am having trouble reaching the desired conversion frequency when attempting to have the ADC convert samples at a frequency of 384kHz( T ~ 2.6us ). The issue I've come across is that on each timer update signal, the ADC first has a wi...

StefanTM by Associate
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  • 1 replies
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Resolved! Strange values when reading timer CNT

I have a timer (TIM10) with a period of 500 us, running without interrupt or any other function.Then I have a rising+falling signal interrupt on PB0 (EXTI0) driven with a 31.25 kHz square wave.In EXTI0 I read the CNT value into a variable New, evalua...

Guidoted by Associate III
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  • 15 replies
  • 2 kudos

STM32H723 .. 735 RM0468 System Architecture table wrong

... or something I don't understand?Looking at RM0468, 2.1 System Architecture "Table 2. Bus-master-to-bus-slave interconnect" shows that DMA1 and DMA2 have access to basically everything except TCM, including APB4 peripherals and SRAM4.Is there some...

LCE by Principal
  • 454 Views
  • 6 replies
  • 3 kudos