FOR STM32H750 QUADSPI, the two banks can work independently?

[yyong]

FOR STM32H750 QUADSPI, the two banks can work independently? can I use bank1 with a nor flash for XIP, bank2 with a nand flash for data?

[Tesla DeLorean]

My interpretation of the docs says NO.

The Dual bank interleaves two identical devices, or dual die packages, to increase bandwidth/throughput.

Suggest you ask your FAE

[Andreas Bolsch]

Not simultaneously: XIP implies memory mapped mode, and this mode requires both devices to have same capacity, same command for read, same number of dummy clocks *AND* a linear address space ...

Of course it's possible to use these alternatingly, as you can select whether to use flash 1 only, flash 2 only and both. But to access the data in NAND flash, you would have to use code in the *internal* flash only and reconfigure the QuadSPI each time, that's probably not what you want to do.

BTW It does hardly make any sense to use memory mapped mode for a NAND flash, as those don't have a linear address space but row/column with column sizes not a power of two (or you have to sacrifice the spare area). Indirect read/write is no problem, of course.

[Imen.D]

Hello,

It is not possible to use two banks independently.

As alternatif, we suggest to use SDMMC with an emmc for data storage.

PS: Please, try to put a summary in "Question" field then details in the body.

I edited your question putting a title that you may change if you want.

Kind Regards,

Imen

[JTse.1]

Dear Imen

can you please show me where in the manual RM0433 does it says that it is not possible to use both flash independently. 

please note that most flash boots up in single spi mode, and i have to use single line mode to switch the flash into quadspi mode

i can do that for flash 1 but cannot access flash 2 independently in order to configure it for quadspi mode as well

also, no matter if it is in single or dual flash mode, 

BK1 IO works correctly and flash 1 works as described in the manual, but not flash 2

the BK2-IO3 (RST) does not go high at all in single spi mode and there is no data on the BK2-IO0 (SDO) so flash 2 cannot be configured at all,

i check on the internet and there are many examples where users use single line mode to simulate classic SPI to reconfigure the flash into quadspi mode

so, if flash 2 cannot be reconfigured, then, how can we make flash 2 to work in quadspi mode.

the manual did not say that i must use special quadspi only flash.

flash 1 works properly, but flash 2 cannot be accessed at all and so cannot be configured for quadspi and even in single line spi mode the rst line is always low, and there is no SDO data, the flash is disabled.

please help, i am really confused why such an important fact is not even addressed at all. please advise, thanks

[Tesla DeLorean]

I don't recall the exact limits of the original STM32H742/743/753, I seem to recollect that I used two parts independently in in-direct/command mode.

For bandwidth they do expect a matched pair of parts in "DUAL" mode where the transfers interleave at a byte level. For example a READ ID (0x9F) would read 6 bytes instead of 3, and bytes would repeat, and reading status you'd read a pair of bytes, and not just one, and you'd need to pattern match the WIP (Write In-Progress) in both of them.

You'd definitely need separate BK1_NCS and BK2_NCS signals to differentiate FLASH1 vs FLASH2

If initial pin states are critical you can configure those pins as GPIO.

There are often multiple versions of QSPI devices, via part number suffixes, that determine the delivered state, and there are often non-volatile configuration registers that make devices stick in a configuration you want them to retain.

The H72x / H7Ax parts have a more complex/refined implementation,and might be sufficiently pin compatible to use instead. The OCTOSPI and OCTOSPIM provide for more options and instances of the peripheral.

[JTse.1]

Dear Tesla

thanks for your prompt reply, i thought so too, even in all other application given out by ST, no mention that the QUADspi needed a matched part when operated in the indirect mode or that the quadspi cannot work independently. in fact, looking at all the examples pin out given, the impression is that it can operate as two independent port as long as all the pinouts is separated except only for the clk. my schematic followed exactly what is shown in ALL the ST example pinouts.

totally separate pinouts for BK1 and BK2 except for only the BK-CLK. BK1 works as expected when i select bit7(FSEL) in CR for flash1 but BK2 does not work properly when i select flash2. the BK2-NCS and the BK-clk works properly, so it is definitely selecting flash2 but two critical pin is not working, io3 which is also the reset pin is alway low and the selected chip is always in reset, and worst,  io0 which is SI do not have any activity at all, it supposed to have the instruction byte from the H743 CPU, easy to see because when flash 1 is selected, the BK1-io0 has that bit pattern on the scope but when flash 2 is selected, BK2-io0 do not have any activity at all, if bk2-io3 is not high and the chip is held in reset and there is no instruction being send, then nothing will work, so this is not the case of wrong circuity, i even checked using just IO mode to toggle the pins, they are all is working. so, this problem is not a hardware issue but a programming issue but after reading the manual more than 10 times in detail, i cannot find what is wrong, i used the exact code that works for BK1 and just set FSEL to select flash 2, as expected, BK1-NCS remains high while BK2-NCS works as expected but yet it does not behave like BK1 at all. this problem seems to be a CPU internal issue and cannot be solved unless someone who has done it explain. I did not expect ST CPU to have such baffling problems. browing the internet, i cannot even find one example of two independently operated quadspi code or config at all. please advise, thanks

[JTse.1]

Dear Tesla

further to your suggestion on configuring the BK2 as IO, i did just that for BK3-IO3 and yes, i am now able to force the rst high and so the chip is no longer under reset

and i also verify again that BK2-io0 which is the SI for the chip is working properly, it can toggle under IO mode

BUT, unfortunately, i cannot use the IO MODE for single line QUADSPI operation,

there is no activity at all when this pin is under control of the QUADspi single line mode.

exactly same code works on BK1-IO0 but once FSEL=1, BK2-IO0 has no activity at all, it should have the same pulse as BK1-IO0 since i am using the exact same code.

so, nothing i can do because it is a ST CPU hardware issue. 

how do i contact a ST engineer or someone who knows this?

thanks