I have an SPI peripheral that generates an external signal (EXTI) when a data record is ready. The data is then read over SPI by the MCU. The data record is 72 bytes.Right now I have an interrupt handler that starts the DMA process to read the next r...
I'm experimenting with bluepill, I have set USART3 to DMA circular mode. I've enabled the HAL_UARTEx_ReceiveToIdle_DMA in the main() and then again in the HAL_UARTEx_RxEventCallback, the half complete receive callback is disabled in both main() and i...
Hello,I am working on stm32h7 series for interprocess communication there is option of OPEnAMP for communication , stm32h7 have asyncronous architecture. There is option for SMP interprocess communication how we can do that?
STM32F301R8T6(Master)M95160-WMN6TP EEPROM(Slave)Low Level driversI've been trying to do a basic SPI EEPROM test based on the STM32F30x_DSP_StdPeriph_Lib_V1.2.3 SPI EEPROM example. Have finally gotten the write to work correctly but when we begin the ...
The DMAMUX1 can trigger DMA requests through synchronization and within the tab of synchronization possibilities there is TIM12_TRGO (input 7). So here is my question do the bits MMS[2:0] in register TIM12_CR2 configure this TRGO (it is written that ...
I declare that I am using a CAN library which works with other boards, so right now I’d like to rule out that’s the problem.Therefore, despite having configured the CAN and the code compile correctly, the messages are not received while using STM32F4...
I have identified from ADC1, 5 channels ( IN1, IN2, IN4, IN11 and IN12) and from ADC2, IN4 which i can use on the Nucleo-F303K8 board. I am currently only concerned with with the ADCs but will later add the 3 DACs ( DAC1/1, DAC1/2 and DAC2/2 ).How d...
I have problems detecting a falling edge external interrupt. I can see with the tester the signal changes from 3.2v to 0v so its produced but the the interrupt is not generated. Could the 3.2v instead of 3.3v the problem?Signal is oscillating 3.19-3....
I read in the reference manual that the STM32H750 has a 32-byte fifo. FTHRES is the FIFO buffer and FLEVEL indicates how many values are stored in the FIFO buffer. The reference manual also explains that after the FIFO is full the QSPI peripheral t...
