I have use stm32l412cbt6 PB9 to input function and i can get the input data,then i configure PB9 to alternate function GPIO_AF14_TIM16 and i can not get the input data.Under the same configuration，PA3 alternate function GPIO_AF1_TIM2 can get the inp...
I'm trying to use the 4K backup RAM on the STM32H743. The RTC is working and keeps time so I know the battery system is OK. I can read and write to the backup RAM OK but it loses all data on power off.I've enabled access as follows:HAL_PWREx_EnableBk...
Hello! I was trying to set aside a section in flash for a variable (I do have a reason to be doing so but, for the time being, I'm in the learning process to make sure I understand how it works before I do anything (too) stupid).Anyway, my chip was t...
Section 5.3.1, Page 85, Table 17 has VDDA min for OPAMP as 1.8VSection 5.3.23, Page 166, Table 80 has VDDA min for OPAMP as 2VWhich is the correct value?I really hope it is 1.8V because that is what all my circuits are designed for...
Obviously copy/paste, probably from 'F40x, ignoring the differences.ST, please fix.JW
I think I found a documentation error in the L412 datasheet. The Quadspi is documented to support two banks in the QUADSPI module description, but I can only find the pins for BK1, which I assume is the first bank. My guess is that the QUADSPI module...
We want to know that which simulator supports for STM32U585.
Histudying the DMA of the STM32F407 MCU, I came across Figure 1: System architecture.It says DMA_PI for GP_DMA1 but DMA_P2 for GP_DMA2.I reckon that DMA_PI is a simple typo and should be called DMA_P1 and stands for the DMA peripheral bus.Would you a...
Hello everyone,I'm developing a firmware for an STM32F767 and I have a problem that happens randomly and I can't figure out why. From what I could analyze looking at the stack I think the problem comes when doing a sprintf and I have the hypothesis t...
Hi,From RM0090 (Rev 19 - February 2021), page 1393:"Host enumerationThe application issues an USB reset (single-ended zero) via the USB by keeping the portreset bit set in the Host port control and status register (PRST bit in OTG_HS_HPRT) for aminim...
