In LPLTIM_IER register, the ARRMIE bit is SET by software and LPTIM_ISR register the bit ARRM bit is SET by hardware but this LPTIM4_IRQHandler() function is not calling. what might be the reason of not calling this function LPTIM4_IRQHandler() ?
Hello ,I recently bought the STWIN.box core system board (STEVAL-STWBXCS1), so I don't know everything about it. I would like to carry out a predictive maintenance project. I followed the steps below:1- flash the binary file with STM32CubeProgrammer2...
I have enabled two interrupts. First one is EXTI for GPIOA0 Pin and another is UART3 for RXCALLBACK.I want to disable EXTI interrupt when UART interrupt is triggered and enable again EXTI interrupt once the task is completed.I used __disable_irq(5) ...
I've generated a CubeMX project for a mass storage class device and can't seem to get the OTG_FS embedded pullup on DP to engage. I've enabled VBUS sensing, and can confirm that the code initially does a soft disconnect (OTG_DCTL->SDIS = 1) then a co...
Here my new code to use encoder with STM32First search on datasheet 2 pins with TIMx_CH1 and TIMx_CH2.In my case was a STM32F469 and I have used PC6 and Pc7 with TIM8_CH1 and TIM8_CH2.After search in the file stm32f4xx_hal_gpio_ex.h the relative AFx ...
Hiwe are working with a STM32H7 project. Recently we upgrade the packages and the Keil.STM32H7xx_DFP.2.5.0 grow up to DFP 3.1.1.Since the upgrading, the SPI start to fail (some data bits were wrong in every reading). Downgrading to DFP 2.5.0 it works...
Hi Team i have one doubt i am using stm32wle5cc controller and stm32wle5cc controller have 256Kb flash memory and each page is 2Kb. and stm32wle5cc controller flash memory support 10k cycles write operations after completes 10k write operations w...
Hello,According to the reference manual RM0456 7.3.3:"Prefetch is enabled by setting PRFTEN in FLASH_ACR.PRFTEN must be set only if at least one wait state is needed to access the flash memory" Compared to that I've seen that in the U5 HAL, in the fu...
Hi everyone.I was struggling with openamp library and finally i couldnt handle it.As i understand this library is built to share data between two cores and as i know both cores have access to the whole memory region.So when we want to share for examp...
We are trying to configure TIM1 and an internal comparator to turn-off the TIM1 complimentary PWM outputs on a falling edge event and generate a TIM1 break interrupt.I was successful to do this with a comparator with Rising Edge event.But when TIM1 ...
