setting source of SYSCLK to PLLCLK affects the behaviour of TIM2

[Ezgi]

Hi,

When I set the clock source of SYSCLK to HSI, I can get the 1 ms timer from TIM2. However, when I set the source of SYSCLK to PLLCLK, I can't get 1 ms timer from TIM2. Why? (The MCU is STM32F407VETx)

I would appreciate any help.

*Edit : The problem was solved.

[Elatewendy]

Hi，

What's the value of Prescaler and Counter Period?

You can calculate the timing time using the following formula：

fclk/(pre+1)/(counter+1)

You can get the clock of TIM2 through the Clock Configuration of CUBEMX.This is the simplest method。

For example:

[Sarra.S]

Hello @Ezgi, 

This is due to the different clock configurations when changing the SYSCLK source from HSI to PLLCLK.

TIM2 is clocked from the APB1 clock, and when you switch the SYSCLK source to PLLCLK, the APB1 clock frequency is different ( you can see that using CubeMX as suggested by @Elatewendy) 

[Andrew Neil]

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@Ezgi wrote:

*Edit : The problem was solved.

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Please mark the solution - so that everyone can see both that it is solved, and what the solution was.