STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...
Hello there, I am making an osciloscope I am using ADC with configuration like thisand I am triggering my ADC with 1ms TIM6 and sending this to PC where I display it I am using 240Mhz CPU Clock and my clock configuration looks like this Now everythin...
Dear All,I am developing an application for USB host mass storage class for STM32U575.I am using STM32HAL APIs for developing USB host and using TinyUSB open-source USB stack.I am able to enumerate flash drive successfully, but not able to perform so...
Dear Members,I am using STM32L4P5VGT, STM32CubeMX 6.9.1, and STM32Cube_FW_L4_V1.18.0.I am steaming data on UART using TX DMA. With the HAL driver, it works fine but do not like to use it due to processing and decided to use the LL driver and had a to...
I installed the STM Studio but i get the following errorHow to solve? Please suggest.
I am looking to add bluetooth onto my project. I have an already developed nRF52 project I could use and just connect it through UART to the STM32H750 or migrate my STM32H750 to a WB based MCU since it has onboard bluetooth connectivity. I was wonder...
Hello,I'm new to STM controllers and working on a project where the STM gets data over serial line from another microcontroller. For this UART1 is turned active and mapped to ports PA_9 (TX) and PA_10 (RX), so data from other controller flows in on P...
Hello,TN1236 explains the advantages of QFN packages with wettabls flanks? Do any QFN STM32 have these side wettable flanks?
I am using STM32U575ZI cortex- M33 controller. I am able to generate a code for the same micro controller in CUBE MX. But in Cube IDE I couldn't able to build the files. It shows some compiler error. like,"../Drivers/CMSIS/Include/cmsis_gcc.h: In fun...
Hello,I am using a STM32H753. I would like to test the ECC on the L1 cache. In my understanding, a double bit error on the data cache would trigger a BusFault: is there a way to produce it? Thank you
