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Hi,I want to use STME32L152 with LSE for RTC.I set the bit LSEON in the register RCC_CSR but the bit remains always 0. I proceeded the same with LSION and it is working well.I disable also the bit LSECSS and behavior is the same.The LSE oscilator did...
Hello,I am using the STM32L053 microcontroller and it is currently communicating with another microcontroller (NRF52 ) through SPI protocol. The STM32L053 is slave and the other is the master.The application consists of :1) The Master(nRF52) sends a ...
We are using an STM32L4S5, and running into an issue with the DMA that is servicing the USART2 RX FIFO. It appears that the USART FIFO is filling up, and the DMA is not able to keep pace. The baud rate is 460800 with hardware flow control turned on, ...
Hi,I'm trying to find out whether there is any way to maintain internal pulldowns on pins in standby mode on the STM32F407.I suspect that this is not the case but haven't been able to find a definitive answer in the documentation. Any help would be a...
Before I enter the stop mode 2 I save all the GPIO MODER, OSPEEDR and PUDPR registers, configure pins as analogue (to save some power) and enter the STOP mode 2. When I exit the stop mode (I use RTC wakeup and GPIOs for that) I restore the above reg...
Hi all,can on the nucleo board is not working.tried using HAL and bare metal.could this be a hardware issue with connections on the nucleo board.for ex. there is a limitation on usart2.the same hal code with appropriate linker works fine for the blue...
I am using stm32f4 discovery board. I will record sound approximately at 5.56 kHZ. So i use 10 bit resolution 480 clock cycle PCLK2 at 21Mhz . When i press the button it will take sample for 10 seconds. Sampling frequency is okay. For 10 seconds reco...
Summary: ADC injected mode has one property that makes it very inconvenient for my use.If an external injected trigger occurs or if the JSWSTART bit is set during theconversion of a regular group of channels, the current conversion is reset.I'm hopin...
I'm looking at the STM32H7 reference manual (RM0433 Rev 5) and the SRAM Mode D writing diagram seems to be incorrect:The data bus should be driven by the MCU and NWE should go low, but the diagram shown is identical to the read diagram.So what are th...
In the RefMan 44.3.8 (June 2018) it says "... depending on DBG_IWDG_STOP configuration bit..." , but this seems to be some STM32F4 remainder ... I think it should better say "...DBGMCU_APB4FZ1_WDGLSD1 configuration bit...".
