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Dear ST-community,I am trying to sample four basebandvoltages simultaneously. Therefor, I trigger 4 ADCs with the same timer in dual simultaneous mode. However, I encountered a problem with the digitized voltages. An image is attached (Y: ADC3, P:ADC...
Hello guys I just want to ask why adding a callback is causing additional time delay to counters. In my case I created a periodic pulse using the PeriodElapsedCallback which is in interrupt mode. I toggle the output every 300ms and this is working ...
Good morningSeems I come a little further with my GPIB Nucleo-F207ZG project where ports stopped responding...The initialization for the SPI1 looks like: hspi1.Instance = SPI1; hspi1.Init.Mode = SPI_MODE_MASTER; hspi1.Init.Direction = SPI_DIRECT...
STM32L152 has 12-bit ADC. How to convert the ADC's digital value into Volt, if there is a 'Vref' reference voltage, and Vref- is grounded? I met two common solution for such ADC conversion:(1) V = CODE / 2^n * Vref(2) V = CODE / (2^n -1) * Vref(CODE ...
Good afternoon (o;Testing a GPIB code on my Nucleo-F207ZG board...GPIB communication is just fine, which uses PORT D and Port E....Now I added SPI code which reads out temperature from a MAX31855 device....using PA5/6 for SPI and PA4 for chip select...
im trying to implement a firmware update via uart on stm32f042.turns out that in order to jump to system memory boot mode in mid program, i need to clear first 4 bytes of the flash (AN2606)also it turns out that it is not possible to delete only few ...
Hi, I am new to STM32 platform. I am using the STM32F439 Nucleo-144 board and STM32CubeIDE. I noticed that in the STM32Cube graphic interface, I can't find anything for SSL/TLS? I did read about Polar SSL but I can't find it anywhere in the interface...
Hello,I would like to know, whether it is possible to configure GPIO pins of STM32F4 MCU family to be interrupted by a pulse signal which has a rising edge and after 100ms followed by a falling edge, like in the screenshot attached. (something like h...
Hi,We designed stm32f7 based custom board and it consist 3 slave devices (FPGA) connected to SPI3 in master mode. when three slaves connected simultaneously & try to access one by one, first two slaves are able to read/write & 3rd slave fail to acces...
Hi,If I configure all AXI-SRAM as write-thru.From the performance point of view, Is the same as disable DCACHE?
