STM32 MCUs products

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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Programing STM32F030 faild: No device at targed

Hi, I designed my first own board with a STM32F030F4P6 on it. Additionally a got me a ST-Link V2 for programing and debugging. As IDEIuse CubeMXIDE. I already successfully programed some Nucleos with it. With my own board I don't get a connection to ...

STM32H7 lowest possible standby current, any examples?

HI!I am currently trying to minimise the standby consumption of a STM32H7 down to theabsolute minimum. Only the change of one Pin (PA0) is selected as wakeup event. No need for backup ram, Pin drivers, RTC nor anything else. The MCU shall only switch...

Microman by Associate III
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Resolved! How to read STM32H7 SRAM ECC status?

I want to periodically check the state of the RAM ECC detection in my firmware on a STM32H753.The ECC mechanism is well described in the Reference Manual for the Flash but not very well (in my opinion) for the RAM.I've seen that there are dedicated i...

Gpeti by Senior II
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STM32L010K4: can't change USART2SEL-bits in RCC->CCIPR

Hi,after encountering the problem with my non-CMSIS-based project, I tried to just set up a simple project in CubeMX, just activating the USART2 and selecting HSI16 as clk-source for the USART.Starting the debugger shows, as already seen in my origin...

GernotM by Associate II
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  • 6 replies
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Resolved! The Purpose of external crystal

Hello everyone, I have a question related to MCU oscillator. Honestly, i usually design MCU with external crystal , by belief that it is surely always better internal oscillator. Even i believed that if MCU isn't run with external crystal will make s...

Setup LI-cache on STM32H753

I'm playing with the L1-cache of STM32H753. What I am trying to do is to provoke -on purpose- an inconsistency between the cache and the RAM as follows: set up the SRAM region as write-through cacheableenable the data cachewrite something to a variab...

Gpeti by Senior II
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  • 3 replies
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