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Use STM32L051C8T6 for low-power design. In standby mode, RTC is used to wake up. The RTC clock is internal 37K clock. After 1Hz frequency division, the program sets 180s to wake up. As a result, it wakes up at 160s. Please ask if there is a problem w...
i am trying to read two timers frequency count and store in DMA , here i have configured two timers in TIM2_CH1, TIM5_CH2 in the input capture direct mode. i used HAL_TIM_IC_Start_DMA() functions to get frequency into DMA . is it correct approach .i...
Hi, I have a Nucleo 144 - STM32H743ZI2 and I need that the output pins deliver 5V, no 3.3V. Is it possible?Thanks
Hi guys,I am trying to optimize interrupt latency and execution speed on an STM32G474.The natural thing is to use the CCM-RAM for what it is intended... while it potentially lowers the interrupt latency, my code actually performs worsewhen executed f...
I am using a STM32F412CGU6 and selected PB_9 to be the CAN Tx pin. The pin then idles at 2.8 volts. If I use it as a standard IO pin, it will go to 3.3 volts. If I assign the CAN Tx pin to PA_12 it also idles at 3.3 volts.I am using mbed 5.12
According to the ordering information, this device provides 2MB of flash.But table 6 on page 77 of the reference manual that shows flash organization for stm32f42xxx devices shows only 1MB of flash, although it says "2 MByte" in the heading. This see...
Hello Everyone!I have thoroughly understood touch sense controller peripheral of STM32F051C8T6, I have also developed a test code using the HAL layer and is working file and detecting touch (i.e. is count value decreasing when finger comes near elect...
I want to add some volatile memory to my MCU (32~64 MB). I'm currently looking at STM32H/F7 devices.Most DRAM needs so many traces that the PCB area taken up by the memory makes it impractical for my design.It seems like there is a new memory interfa...
I wonder if STM32H750 will work with QuadSPI PSRAM chip (for example ESP-PSRAM64H) and map it into the memory natively? I've read in the datasheet that MCU supports Flash chips via QuadSPI, but what about PSRAM?