Can anyone point me to "soft error" stats on the STM32L452 SRAM and Flash arrays? Lacking that, can anyone tell me what design rule/geometry the SRAM and Flash arrays use (in nm), from which I can estimate the stats?
Can anyone point me to "soft error" stats on the STM32L452 SRAM and Flash arrays? Lacking that, can anyone tell me what design rule/geometry the SRAM and Flash arrays use (in nm), from which I can estimate the stats?
Re: Can anyone point me to "soft error" stats on the STM32L452 SRAM and Flash arrays? Lacking that, can anyone tell me what design rule/geometry the SRAM and Flash arrays use (in nm), from which I can estimate the stats?
