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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Resolved! STM32G0 - Initial PWR register settings

Checked PWR settings at startup.Find PWR->SR2 status value 0x00000300.According manual this tellsRegulator in Low Power mode (LPR)Flash memory in power downIs this initiated by Keil/ST-Link debugger?Or are there errors in reference manual of register...

JuM by Senior
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STM32F303RETX synchronous Buck converter hint.

Hello, I am designing a Buck converter to control two Peltier heating or cooling mode. I found nothing available from market, so I designed mine. Target stable temperature, logging and alarm. It control a vaccine VET fridge, stable control temperatu...

MCU STM32L562: With initialising the UART using HAL_UART_Init() the UART-communication is not working. Calculating the BRR like shown in the reference manual gives a working BRR-Value. Is the HAL_UART_Init() not intended for setting the BRR ?

The Project was migrated from STM32L4 to STM32L5. The Baudrate setting with HAL_UART_Init() works fine with L4 MCU. With L5 MCU it returns with an HAL_UART_ERROR_NONE too.

PKM by Associate II
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reg addr's for GTZC_TZSC_MPCWMxANSR GTZC_TZSC_MPCWMxBNSR

The doc and SVD file don't have a reg at offset 0x44 (GTZC_TZSC_MPCWM3BNSR).Since GTZC_TZSC_MPCWM3ANSR @0x40 exists, via symmetry I would expect B also at 0x44.The doc does say this:GTZC_TZSC external memory x non-secure watermark register 1(GTZC_TZS...

Hedley by Associate III
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Single digit year in date code may be inadequate

The STM32 have a 3-digit date-code timestamp, in YWW format, with single-digit for year.Given the rolling 10-year longevity commitment, this may be not adequate to uniquely identify the manufacturing year, e.g. in light of ES0204 Rev 10 2.3.8 (The d...

Resolved! LED LD2 on STM32h745ZI-Q Nucleo 144 board not working

Sorry this is a very simple question but somehow LED LD2 just won't work on STM32h745ZI-Q nucleo 144 boards. As per the manual "UM2408 STM32H7 Nucleo-144 boards", the LD2 is connected to PE1 (by the way, I tried PB7 as well as the older one may on th...

ADC channel 12 less accurate than the other ?

Hello,Since two year, I am experiencing an issue with the ADC_CHANNEL_12 (pin PC12) of my STM32F767. I suspect it's a hardware issue coming from the MCU. a stable offset is added (randomly change each time I reboot the STM)this read value (via DMA) i...

jean by Senior
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