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Is it possible in the STM32 world to have two synchronized PWM - but with an offset separating the outputs?Here's the problem in picture form:Both the blue and red traces are the same frequency and duty cycle, but in this case trace red is offset 50 ...
Dear Madame or Sir.We found some errors in HAL-Driver "stm32h7xx_hal_fdcan.c" Version 1.10.0.0:for the FDCAN modul of STM32H743.stm32h7xx_hal_fdcan.cA call of the function "HAL_FDCAN_DeactivateNotification" and"HAL_FDCAN_TT_DeactivateNotification"CAN...
STM32H743Does errata 2.16.2 "Wrong data may be read from Message RAM by the CPUwhen using two FDCANs" apply to silicon revision V?The errata indicates it does, but previous discussion by Imen Dahmen indicates the issue was corrected. I need a confirm...
The errata sheet of these MCUs says:2.16.2 Wrong data may be read from Message RAM by the CPU when using two FDCANsDescriptionWhen using two FDCAN controllers, and the CPU and FDCANs simultaneously request read accesses from Message RAM, the CPU read...
Hi, I always appreciate all members here for helping beginners like me :)I am currently working on a project using Timer and ADC+SPI with DMA.The main timer loop is running at 40kHz, and this frequency should be strictly guaranteed.Two DMA process...
I'm checking the ADC operation with STM32H7B3I-DK board.To set adc clock frequency up to 50MHz, i tried to change BOOST bits of ADC_CR register.However, unlike the rm0455 document that states that bits 8 and 9 (BOOST bits region) can be set, when ...
HelloI am trying to delay a 1Hz digital signal.I would like to generate a delay varying from a few microseconds to 10 ms.I tried to use ETR, TI1_ED and PWM input but I didn't manage to found out how to do.Does anyone has an idea on how to proceed?Bes...
Error :Messages for model XXXX：Vmeas_(rising/falling) is set,It is necessary for delay neasurements. satisfy Vinh >= Vinl.
I am exploring the memory space of my STM32F051 using a very simple hex monitor that communicates through a serial port. I can (attempt to) read/write a byte at any arbitrary address in the 32-bit address space. Within the SRAM area (starting at 0x20...
