Resolved! PLL clock division in STM32H7 for fadc_ker_ck
Hi,a footnote(4) in STM32H7 reference manual RM0468 Table 56 regarding the maximum allowed frequency for ADC says"With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even".Does this recommendation apply to the actual DIVXx regist...