STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...
Hi everyone,I think like most people, I ignored the errata sheet till it was too late. I know that the stm32f4 and quite a few others do not provide hardware support for TTCAN, which as far as my understanding goes is level 2 CAN (global time synchro...
Hello Every One!! I am Using NUCLEO G0B1RE Board, facing Issue with CAN Receive Function I am using MICROCHIP CAN BUS ANALYSER and NUCLEO BOARD for CAN Communication void CAN_Recieve(void){ while( (HAL_FDCAN_GetRxFifoFillLevel(&hfdcan1,FDCAN_RX_FIFO0...
I've synchronized TIM3 and TIM4, the TIM4 being triggered when the TIM3 Output Compare No Output on channel 2 is active. I've configured the TIM3 channel 2 as "Output Compare No Output"In order to control the time delay between TIM3 and TIM4 activ...
I am working on a custom board equipped with an STM32H753 and a SD-Card connected via SDMMC 4bit wide Bus. FreeRTOS is used. HAL is generated using CubeMX and the package "STM32Cube FW_H7 V1.9.1".CubeMX generates the file sd_diskio.c and in it (line ...
I need a clarification regarding the actual ADC code equation for SAM4S family of microcontrollers. The equation from data sheet is,Does this equation hold good for both single ended and differential inputs ?Looks like it is considering a differentia...
I am using LPTIM for periodic ADC reading (every ~250ms) and periodic IWDG refresh. CPU should go to Stop mode when the ADC value is under certain value. If the ADC value is over certain value then CPU should reset end continue in Run mode. ADC is cl...
I am working in a project where I have to sample a signal with a sampling frequency of 8 kHz with the ADC. That data is send from the ADC to SRAM using DMA and then send through UART interface. I am using a "Blue pill" board (STM32F103C8T6) with a sy...
They don't make DRAM QSPI chips in an SO-8 package with more than 64 Mbits (maps to 2 Mbytes * 32). Given the current processor shortage, I've got an application where I'd like more memory (and I'm using a 100 pin package which is quite pin limited,...
The errata sheet of the STM32F042 states:The time-triggered communication mode described in the reference manual is not supported. As a result, timestamp values are not available. The TTCM bit of the CAN_MCR register must be kept cleared (time-trigge...