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Hi,We have a custom board based on STM32H755. We have two configuration of this SoC. In the normal operation we run a Bare-metal application on M7 and Zephyr OS application on M4 in a dual core mode. When requiring firmware update, we run a Zephyr ap...
I have a STM32H755 based board where we use M7 for BareMetal and M4 to run zephyr OS. We enabled IWDG1 in BareMetal and finds that the Flash erase of Bank 1 (M4 bank1, M7 bank 0) from Zephyr cause a reset and reset cause is IWDG1. Couldn't understand...
Can M4 write to part of Bank 1 when M7 code is running from Bank 1? Idea is to define apartition at the end of Bank 1 and M4 write to it while M7 reads from it. I know thisneeds some tweaking of the dts to assign both Bank 1 and Bank 2 to M4 as below...
Hello experts,I have a requirement to use M4 to write to flash partitions under Zephyr OS. Currently Flash controller driver doesn't support M4. So I have a pull request being reviewed here https://github.com/zephyrproject-rtos/zephyr/pull/65250What ...
Hi support,I am trying to have STM32H755 boots simultaneously with following use case and seeing that CM7encounter an infinite loop execution at 0xa05f0001 for some reason. Could someone help me tounderstand why this is happening and what is wrong wi...
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