I am using cube mx for my design and I have some peripherals (ADC, Timer, I2S2, I2S3). I am making streaming by usb of some of them. I want to stoop i2s modules when i am not using it becouse affect to other modules sampling rate.By default Cubemx m...
Hi ! I am receiving data through UART using DMA to a buffer of 10 bytes. I want to always receive to the uartBuffer[0]. Thank you!
I am trying to implement a Phase Locked Loop in a microcontroller STM32. I have a reference signal and feedback signal which has $\phi$ difference wrt reference signal. For the moment, I am not using a real time feedback signal, rather simulating it ...
I use ADC2 and ADC3 (with HAL_ADC_Start_DMA) with no problem, just having problem with ADC1. I'm using FREE-RTOS. STM32CUBEIDE.
uint32_t write_to_flash(uint8_t * buf, uint16_t length){ if((length)>2047) return 0xFFFFFFFF; uint32_t base_addr=0; base_addr=getHexAddressPage(DATA_PAGE); uint32_t PAGEError; /* Unlock the Flash to enable the flash control register access ...
Hello.I can't find Glitch value for DAC in the STM32G071 documentation, and also what type of DAC is implemented in the MCU: R2R, resistor string, etc.Where can I find the information I need?
Hi, I have a problem with starting a stepper motor using the I2C bus. It uses the NUCLEO-F746ZG microprocessor, the SMC 64-BP stepper motor driver and the KH1634-03CA stepper motor. The main problem is finding the address of the controller and giving...
I am developing a card with a supercap storage, I designed it for a consumption of 40uA as it is written in the datasheet, however I reach only 3mA and I use the "standby" mode written and found on the internet. Can you explain me how to disable the ...
In the errata sheet,it is mentioned that low drive mode and medium low drive are not working.. but I checked and they work fine...is there any correction in the errata sheet...?..Can I go with low drive mode for LSE (NUCLEO-U575ZQ)???
I connecting an FPGA slave to an STM32F7 FMC 'sram' bus. For this particular project, I need to access the bus both inside and outside of an interrupt. Because there is a write FIFO, can I assume that writes are atomic and don't require mutual exclus...
