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Hello everyone, I am working with an STM32H753ZI board and I want to set up CAN communication. I’m a bit confused about what changes I need to make. Here are my main questions: Does the STM32H753ZI use the regular CAN peripheral or the newer FDCAN p...
Hello, I am working with an NUCLEO-H753ZI (ADC1/ADC2 with DMA1/DMA2, and ADC3 with BDMA).My goal is to store ADC conversion results directly into a uint32_t buffer using DMA, so that the 16 valid bits from the ADC are automatically ...
Akkording to AN3155, July 2025: "The highest tested baud rate (BHigh) is 115200." Have tried with 921600 and that seems to work fine. Is the recommodation from ST that not use above 115200?
HiI modified nBOOT_SEL Bit, but still the PA14-BOOT0 Pin level has no effect. The CPU starts always on in Main flash memory. I have these 2 situations (RM0490 Rev 5 page 53) If PA14 is low level: Main flash starts. This is okIf PA14 has high level: ...
hi,The PCB with STM32F746zgtx has already been shipped to the customer.Pin PA12 is responsible for controlling the RS485 DIR.The documentation states that Pin PA12 is powered by the Vddusb pin.It turns out that pin PA12 doesn't drive the high voltage...
The new STM32L4R9 svd file (version 2.0) has renamedTIM1_OR2 to TIM1_AF1,TIM1_OR3 to TIM1_AF2Removed TIM1_OR1 which is in the reference manual containing ETR_ADC1_RMP and TI_RMPAdded a new TIM1_TISEL at offset 0x68 which is not in the current referen...
Hello everyone,I am facing a strange behavior when using ADC scan + DMA with an STM32L476RG.To debug the issue, I created a very simple test code: the MCU performs a scan measurement on 4 channels of ADC1 (PC0, PC1, PC2, and PC3) using DMA.Test setup...
I have a small project which should generate an interrupt whenever a DMA transfer has completed. If I build the code for an STM32F411 then it works exactly as expected. If I build that same code for an STM32F401, which is within the same family as ...
Hello,I want to use the Timer1 CH1 and CH1N of the STM32H563ZI with dead time generator and break input functionality. It should behave in that way that when the break input (BKIN) is triggered it should goes to a predigined idle state (for CH1 low a...
In STM32G474.svd version 2.1 that can be download from STM32G474RE product page , WWDG peripheral has no interrupt defined but it is actually the first (0th) interrupt. Is this a mistake or there is a reason behind not defining it in the SVD ?
