Register: RCC reset duration control register (RCC_RDCR)
Bits 27:24 EADLY[3:0]: External access delay The bit field is security-protected by the 1 bit. Set and reset by software. Time to wait before the BOOTROM performs any external device access 0000: No extra delay added by the BOOTROM 0001: 100 μs 0010: 200 μs 0011: 500 μs 0100: 1 ms 0101: 2 ms 0110: 5 ms (default after reset) 0111: 10 ms 1000: 20 ms 1001: 50 ms 1010: 100 ms 1011: 200 ms 1100: 500 ms 1101: 1 s 1110: 2 s 1111: 5 s