STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...
The new STM32H7R/S lines are built on the success of the STM32H7 series, offering even higher performance and security at a lower cost. The STM32H7R/S is a bootflash-based MCU powered by a Cortex®-M7 core running up to 600 MHz, with 64 KB of user fla...
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Hi allI'm trying to distinguish between the interrupt sources in the NMI handler on a STM32G031 - particularly the RAM parity error.I have everything in place and I can provoke a parity error. The NMI ISR is called as expected, but if the SYSCFG_CFGR...
I am working with STM32L010C6T6 MCUs. I need a way to consistently and uniquely identify each MCU with as few bytes as possible. The 96 bits "Unique device ID" register seems ideal but what is the minimal number of bytes I need? Are all 96 bits manda...
I´ve read some MCUs support idle line events, but looking through the datasheet can´t see how to implement this.I could DMA 3 bytes at a time, but best would be to have DMA completion triggered after idle or timeout.
I think there is an error in the PM0214 Programming manual "STM32 Cortex® -M4 MCUs and MPUs programming manual". The multiply and accumulate instruction is called "vlma" throuout the whole document. Other programmin manuals (e.g. for STM32H7) as well...
I have a STM32-G071RB. I want to generate two sine outputs. one for reference and the second with a phase shift. Unfortunately, there is only one DAC port. I got an extra board but then I realized I need communication between the two boards to (I fou...
HelloI am trying to communicate with a Daly BMS in UART. I tried at first with an arduino board where I got the desired frame but when I tried with a custom made STM32F072 board. But during this test I can't get any response from the BMS.The BMS work...
[Solution] Code was moved around and then it compiled correctly. Misinterpretation of the problem.IOC Configuration: Pin PB9 - External Interrupt with Rising/Falling Edge trigger detectionPull-DownNVIC EXTI line [9:5] Enabled Preemption Priority 1 Su...
I think there is an error in the reference manual (RM0440 Rev 7) in chapter 24.5 - COMP interrupts.At the end of this chapter it says: "Interrupt events are flagged through COMP_CxCSR flags."But in COMP_CxCSR register there is no flag for interrupt e...