About ADunc.1

ADunc.1 · 2023-06-05

I have been stuck on a tricky little issue for some time now.Using an STM32H753, on a reasonably large and complex application, when trying to erase the upper flash bank, the watchdog expires resetting the chip!My suspicion is that the CPU is stallin...

ADunc.1 · 2021-02-10

STM32Cube MX Version 6.1.1, STM32Cube MCU Package for STM32H7 Series V1.8.0eth.c is generated with the following code. It sets the MAC address assuming it is an array of bytes./* ETH init function */ void MX_ETH_Init(void) { heth.Instance = ETH;...

ADunc.1 · 2020-05-04

I have been battling an issue for a while where upon a watchdog (WWDG1) timeout, the system was not correctly reset. I was finding that the CPU and NVIC are reset but all the peripherals are not reset after a watchdog reset, they keep their exact reg...

ADunc.1 · 2020-04-27

I have repeatedly observed that changing the watchdog prescaler on a running watchdog from 16 down to 4 usually causes the watchdog counter to eventually stop decrementing. I assume this happens due to something like decreasing the prescaler value b...

ADunc.1 · 2023-06-05

Thanks for your ideas. Here is my progress on them so far:Yes the core should stall if it attempts to read or execute from a flash bank during its erase.The code to enable an MPU region to detect accesses of the upper bank during its erased could be...

ADunc.1 · 2022-11-09

A also cant get kernel aware debugging working. I have working debugging, SWV works (but is disabled). When I try enable kernel aware debugger settings, I get the message below when trying to start debugging:Using STM32H753, ST-Link V3, FreeRTOS. ...

ADunc.1 · 2022-11-09

Thanks @GLASS . I was under the impression that if LSE was already on, then there was no significant time lost waiting for LSERDY to be set. The CubeMX code just sets bits the LSE register as needed (which will be exactly the same as the previous ...

ADunc.1 · 2022-11-09

Thanks for your feedback @Amel NASRI . Unfortunately a hardware workaround will not stop our products that are already in the field from having this issue. A lot of these products were shipped before the errata was even updated with mention of thi...

ADunc.1 · 2022-11-08

Thanks everybody for your answers.I did check errata and saw the issue about LSE driving bits swapped. I also noted in the STM32H7 cube library that the macro to set oscillator driving capability checks device revision and the swapped bits only appl...

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STM32H7 WWDG expires during Flash Erase

STM32CubeMX STM32H7 Ethernet MAC Initialization is Broken

STM32H7 watchdog does not correctly reset. Example attached

Why does changing WWDOG prescaler stop the watchdog counting down?

Re: STM32H7 WWDG expires during Flash Erase

Re: FreeRTOS RTOS Kernel Awareness not working on CubeIDE 1.8.0.

Re: Dead LSE and PLL

Re: Dead LSE and PLL

Re: Dead LSE and PLL