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Posted on February 02, 2018 at 21:28 \STM32Cube_FW_L4_V1.0\Drivers\BSP\Adafruit_Shield\stm32_adafruit_sd.c Issue with ReadBlocks/WriteBlocks on SDHC cards, offset advances in BlockSize!!! ReadAddr should increment by 1. The current routine del...
Hi,I am building a product where I have to store calibration data and retain it even after power off.I am using the STM32H745ZiT6 and would like to use its flash to read/write data. As I have setup communication between the two cores I have the curre...
I’m experiencing an issue while developing firmware on a STM32L431CCU6 connected to: Xbee module (XB3-24Z8CM-J) via UART1RS485 driver (ST1480ABDR_ Via UART2 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); HAL_NVIC_EnableIRQ(USART1_IRQn); HAL_NVIC_SetPriori...
I'm trying to use the HRTIM TimerA on the STM32-G474 to generate a one pulse on TA1 output in response to an external event on hrtim_eev1.I need the pulse to be generate with low latency and low jitter, but I'm not being able to get the Fast mode wor...
Hello we Have Custom Build PCB Board where we Mounted SD card Interface and Using stm32f4xx_HAL_SD.c Library file in which 512 byte Hard Coded as config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;, but we have to write Byte means don't block size of ...
Hi everyone,I'm facing an issue with using DMA1 for SPI communication in my project. I'm trying to achieve a 2 kHz frequency, but DMA1 doesn't seem to work at this rate, whereas BDMA functions without any problems. This is my sampling task that is ca...
I am trying to use second half of OCTOSPI pins in single memory mode by setting MSEL bit for QUAD SPI communication with Flash memory. Even though i set the MSEL bit to send the data through 7 to 4 pins, still data is going through the 3 to 0 pin onl...
Upon selecting the directory:C:\Users\myname\STM32Cube\Repository\STM32Cube _FW_L4_V1.11.0\Projects\NUCLEOL476RG\Examples_LL\ GPIO\GPIO_InfiniteLedTogglingI am unable to see the project file:GPIO_InfiniteLedToggling\SW4STM32 \STM32L476RG_NUCLEOAlso, ...
Hi, my program required a large amount of RAM memory, how can i know which external memory i can choose? and which peripheral is dedicated for this?
We encountered an issue with the SPI3 peripheral on F4xx and F7xx series chips where the RXNE bit of the status register would be set right after enabling the SPI peripheral after re-configuring it.This is clearly impossible as no transaction is perf...
