STM32 MCUs products

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Resolved! Do the G4 series contain a DMA on timer break feature?

The RM0440 ch. 28.3.18 rev7 mentions on page 1128:> An interrupt is generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set.Unfortunately, the DIER register does not contain...

Loebl by Associate II
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Stm32f103c8t6 RTC Crystal Choice

Hi, I'm trying to do embedded 103c8t6, and I'm having some trouble with selecting the right crystal.Here is my Schematic. I'm using ABS07-32.768khz with 12.5pF load Capacitances and the equivalent series resistance is 70kR. I took Cstray as 5pF that'...

0693W00000aIpbIQAS.png 0693W00000aIpcuQAC.png
CArda.1 by Associate
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Resolved! Older STM32H743ZI MCU Nucleo board was updated to V3.J10.M1 firmware version. While The board can be flashed, it isn't possible to debug or erase chip memory. Is there a way to roll back the update?

After running into some issues during an OS migration, I ran a firmware update on a nucelo_h743zi board using the stLink utility. After this I ran into many issues with flashing and debugging. While I can flash the board with openocd v11, it has some...

GToml.1 by Associate
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STM32U575: is it possible to disable blocking the read and write accesses to the backup registers, backup SRAM and SRAM2 when the tamper flag is set? To use tamper input for information and not security purpose.

According to RM: "In the NOERASE configuration (TAMPxNOER=1 in the TAMP_CR2 register, ITAMPxNOER=1 in the TAMP_CR3 register), the backup registers and other device secrets are not erased when the corresponding tamper event is detected. In addition, t...