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Hi I want to improve the FPS of TFT when using SPI interface.I use SPI+DMA+QuadSPI PSRAM+QuadSPI Flash for now.I notice STM32L4P5RG has DMA2D.So can it use for SPI interface?Will it have any improvement when I refresh TFT?If it has, how to use it?
Hello. I've a problem regarding LSE On stm32l562xx mcu. Sometimes it boots, sometimes it doesn't "90 % of time it generates timeout Error" . and it takes too much time to boot up to 4 seconds. I've tried all your sdk initializations, also tried setti...
I find that flashing a program using openocd, STLink (using a Nucleo F446, or L474), to our custom board frequently fails when there is CAN bus activity. What is causing this?Our board has BOOT0 tied to ground. The SWD is gnd, data, clock, and connec...
Hello, everyone this is my first post here.I'm starting to learn Embedded Programming and I choose STM32F103C8T6 using Blue Pill development board. I'm trying to understand SPI communication, my goal is to read multiple input using 74HC165 IC. I'm ab...
I'm using the STM32G030C8 for one of my projects and i realize that in some cases the RTC stops when the power supply is up. While in VBAT supply the resonator works well and provide the correct date and time, but when i use the power supply the reso...
Per the presentation linked below, the independent watchdog timeout range for the SMT32H7 is from 125 microseconds to 32 seconds. Is 32 seconds a hard limit? We would like to increase this value.STM32H7-WDG_TIMERS-Independent Watchdog (IWDG)Thanks in...
Hi,We are facing some challenge with external watchdog timer and STM32H7855xi. when there is no program in flash input to external watch dog timer (WDI) is output and no pulse . during this time external watch dog timer continuously generate reset pu...
Hi,I am trying to make a program in which in the micro stm32u5 is stored in ram memory some data after activating the Sleep Mode. For this I have defined in the flash file the SRAM2 memory which is the one that is supposed to be in charge of this: ...
Currently I'm able to run ADC1 and ADC2 in interleaved mode using seperate (on purpose) DMA channels for ADC1 and ADC2. To start I'm using: SET_BIT(hadc2.Instance->CFGR, ADC_CFGR_DMAEN); //Enable DMA transfer for ADC slave (ADC12_CCR.MDMA = 0b00 -> ...
Hi everyone, I facing some issues with the custom flash loader tool and MCU, I developed the tool and bootloader code of the STM32H503RBt6 controller, and I flashed the hex file using the custom tool, its works but the data is not flashed in the cont...
