About KHarb.1

KHarb.1 · 2024-07-11

I set the X1 buffer size to 18 and preloaded it with 18 values. HAL_FMAC_FilterPreload_DMA returned 0 indicating success.Some cycles after that, I should see X1FULL go high when the DMA transfers complete. I'm not seeing this. Instead, X1FULL stays l...

KHarb.1 · 2024-07-07

I have an application requiring updating the integral and derivative values for a set of PID controllers. Each arriving error value must be added to the integral value and subtracted with the last error value. I want to streamline this with DMA. I c...

KHarb.1 · 2024-07-07

I’m using CubeIDE + HAL and I want to have TIM20 CH1 execute a capture compare interrupt and I want CH2 to execute a DMA transfer. I can use each separately, but together they fail. Either the timer resets stop functioning, or the counter stops count...

KHarb.1 · 2024-07-03

I have the FMAC working enough to produce values readable from RDATA, but they are acting strangely and giving small positive and negative values and 0. As a minimal test, I created the below code to have X1 and X2 be all 1s. A buffer length of 18 sh...

KHarb.1 · 2024-07-02

I've finally got the FMAC to load, execute and produce data. However, I can only make the X1full flag get set if I call 16 writes to WDATA. I'd like to streamline part of this and use a memory to memory transfer. I'm seeing this not working. Can memo...

KHarb.1 · 2024-07-07

Good. I guess it appears HAL\Cube doesn't...so I need a working code fragment where it's configured manually. Any pointers to a reference project?

KHarb.1 · 2024-07-06

This issue had to do with least significant bits being truncated. Multiplying the test value by 0x100 produced the expected output.

KHarb.1 · 2024-07-05

I don't follow. FMAC->WDATA is a mapped register I want to write to repeatedly from values held in an array that is stored in SRAM. Where's the confusion?

KHarb.1 · 2024-07-02

Right...that's only confidence though. I'm going to be adding more and more DMA channels and traffic, it could get really hard to test if the order isn't consistent, hence the the search of definitive info.

KHarb.1 · 2024-07-02

I guess these bits do not act as they do in the documentation until a calculation operation is started. Between the pre-load and the operation init, it appears undocumented behavior takes place.

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FMAC DMA preload returns 0 but X1FULL is never set and YFULL behaves strangely

Is the CORDIC coprocessor microcoded and can it be modified?

Can a timer be configured with interrupts and DMA active?

Minimal FMAC gives wrong answer on STM32G4

M2M DMA transfer to FMAC->WDATA fails, but individual writes to WDATA work. Is M2M supported for loading X1?

Re: Can a timer be configured with interrupts and DMA active?

Re: Minimal FMAC gives wrong answer on STM32G4

Re: M2M DMA transfer to FMAC->WDATA fails, but individual writes to WDATA work. Is M2M supported for loading X1?

Re: Is priority gauranteed to make two DMA transfers initiated by the same trigger arrive at a static destination address in order?

Re: FMAC writes YEMTPY and UNFLs bit incorrectly after pre-loading X1 coefficients with no reads or executes taking place. Why?