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STM32N6 IMX219

Hello,I'm trying to port the ST IMX335 camera driver middleware to work with the RPi 2 IMX219. Everything works well with the IMX335, however after adjusting to reflect the IMX219 registers I get no image data and a Lane 0& 1 control error flag as so...

STM32F407 I2C ADDR bit not being set

Hi, Im using my own I2C library but after i write the device adress when i receive SB interrupt the adress bit never seems to be set to 1. I have tried testing it with HAL and it seems to work fine. I would be happy if someone could helpvoid I2C_Even...

STM32H5 I3C dynamic address assignment

hi:I have two NUCLEO-H563ZI EVB boards  and tried to implement I3C controller and target feature.When ENTDAA was issued, I obtained the target 48-bit provisioned ID "0x020813810100" from waveform, I saw the description from I3C register  I3C_EPIDR ,i...

Garry by Associate II
  • 3795 Views
  • 13 replies
  • 6 kudos

STM32U5 Burst length vs FIFO size

Hi all, i am going through deeper configuration of GPDMA on STM32U5 and there are some things i do not understand.S/DBL_1 in TR1 register is able to vrite destination/source burst length in range 0-63 but FIFO size is 8 bytes for channels 0-11 and 32...

Eiffel by Senior
  • 190 Views
  • 3 replies
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Resolved! FDCAN tx & rx FIFO size

Is there a way to set the FDCAN TX and RX FIFO sizes for STM32H7R7 in CubeIDE?I snooped around and found a list of macros that are responsible for determining the FDCAN RAM size in the stm32h7rsxx_hal_fdcan.c. Do I just modify these values to set the...

Screenshot 2025-09-13 at 12.44.55 AM.png Screenshot 2025-09-13 at 12.36.12 AM.png
Kwame by Associate II
  • 225 Views
  • 3 replies
  • 1 kudos