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Hi, req is generate sine wave and manage frequency precisely . My design require range 2Hz to 10Hz with for example step 0,002Hz.My idea is one PWM timer for sine with same table for exampel 10bit. Second linked timer for manage one sample time on PW...
Hello, we intend to implement a time-dependent channel change via the operational amplifier in voltage follower mode, as described in AN5306 - Rev 1 Page 31, 5.1. However, when checking the output, there is an unwanted gain (x2) on channel 2. Any ide...
Hello everyone. I am currently working on a bootloader with a STM32H743VGT6.I need to write data on both banks which aren't continuous as you can see below: It was recommended in this topic to use HEX format, but I need to stick to bin files. So my ...
Hey guys.I need to enable/disable the line 14 of the EXTI interrupts multiple times, using HALDo i just use the HAL_NVIC_DisableIRQ HAL_NVIC_EnableIRQ ( and HAL_NVIC_SetPriority whenever i re-enable the line?), providing the correct handle to the a...
I'd like an opinion on this issue with timers; I have working code, but it took me a while to understand that the code was actually working (though not while debugging).I'm using STM32F446RT.I'm configuring two timers so that one timer is a master, a...
Hello everyone.I am having trouble reaching the desired conversion frequency when attempting to have the ADC convert samples at a frequency of 384kHz( T ~ 2.6us ). The issue I've come across is that on each timer update signal, the ADC first has a wi...
I am studying STM32 timers (I have a Nucleo F446re) and I am wondering what is a use-case for this configuration Slave Mode: DisabledTrigger Source: ITR0Clock Source: Internal In my understanding you use ITRx when you want to cascade timers (i.g. TGR...
I have a timer (TIM10) with a period of 500 us, running without interrupt or any other function.Then I have a rising+falling signal interrupt on PB0 (EXTI0) driven with a 31.25 kHz square wave.In EXTI0 I read the CNT value into a variable New, evalua...
... or something I don't understand?Looking at RM0468, 2.1 System Architecture "Table 2. Bus-master-to-bus-slave interconnect" shows that DMA1 and DMA2 have access to basically everything except TCM, including APB4 peripherals and SRAM4.Is there some...
Dear Team,Currently, we have developed a prototype with an ESP32 and the prototype meets all the functionalities. However, we are now having some troubles scaling it to production. So now we are looking to migrate our product to using STM MCU. We hav...
