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When using RTC, the GPIO pin state of PA4 may be corrupted. RM0454, section 23.3.3 says: "In addition, it is possible to output RTC_OUT2 on PA4 pin thanks to OUT2EN bit. Thisoutput is not available in VBAT mode. The different functions are mapped on ...
Hello everyone,I and my collegue have more than 20 years experience on embedded desing with MCUs. We have a problem which we haven't seen this kind of problem before. I guess someone can help us in here.MCU: STM32F756IDE: Project created from cubeMX ...
This is a question about Receive Only Master (SPI_DIRECTION_2LINES_RXONLY).I was able to output the waveform shown in the attachment using Receive Only Master.However, no data is being received(tmp). Why is this? The process is performed in the foll...
The reference manual 0433 Rev 8, p. 900, section 23.5.5 says "This bitfield has no effect when in memory-mapped mode (FMODE = 10)." But p. 901, section 23.5.6 says: "11: Memory-mapped mode".Could someone please let the authors fix this?Thank you.
Hello,I have an ISR for TIM4 running on an STM32F2 microcontroller. The ISR triggers on a rising edge of the timer input channel, and its purpose is to record the microsecond timestamp of the last two rising edges in global variables for other parts ...
Hi,I'm using STM32G474 to drive my BLDC motor, i want to trig low-side phase current sensing ADC when the lower MOSFET is conducted. But the wired thing is even though CMP2 callback did be called by interrupt, ADC also not triggered (ConvCpltCallback...
Hi Foued,I'm going to connect 10 BMI323 IMUs to STM32H503RB MCU by I3C bus. BEI323 supports I3C and dynamic addressing and 0x68 static address. Is it possible for I3C bus of STM32 to recognize all IMUs by assign different I3C addresses to make all of...
Hi AllI have created a PCB where I want to use the OCTOSPI to communicate with a FPGA.I have difficulty finding accurate information on how the different memory types work. I already have a Hyperram running so I started there, that did also seem stra...
Regarding the problem that CTSIZE becomes 0x01 after SPI communication is completed,In our program, SPI-SR-CTSIZE becomes 0x01 after SPI communication is completed.In that state, if we try to perform the next SPI communication, a timeout error occurs...
[This is a reconstruction of a thread I've started on Mar 26, 2017, but got lost in the two forum software transitions since then.]Reports in IWDG short period (125 us) problem and STM32F407 : IWDG and erase flash sector indicate that the IWDG does...
