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STM32H573 I2S audio clock problem



I'm trying to set the following parameters for I2S in Device Configuration Tool (STM32CubeIDE v1.14.0):

- Master Clock Output enable

- audio frequency: 48kHz

- Data and Frame Format: 16 bits

I want to connect an external 12.288 MHz clock to the AUDIOCLK input, but I get the following message:

"With this I2S Clock (12.288 MHz), the divider value (0) is too low to obtain the desired Audio Frequency (48.0 kHz). The I2S Clock must be higher than (43.008 MHz)."

The problem is that according to RM0481, the I2SDIV may have the value 0:

"I2SDIV can take any values except the value 1, when ODD is also equal to 1".

A similar problem was described here:

however, in that case in RM0090 the value 0 and 1 were actually forbidden for the STM32F429 in the I2SDIV field. For STM32H573 such values are allowed:

"CHLEN and ODD can be either 0 or 1. I2SDIV can take any values from 0 to 255 when ODD = 0, but when ODD = 1, the value I2SDIV = 1 is not allowed. When I2SDIV = 0, then {(2 x I2SDIV) + ODD} is forced to 1."

Is this a CubeMX/STM32CubeIDE bug or do I really need to use a higher clock rate on the AUDIOCLK input?

Principal III

i just tried (in Cube) , with external 12,2M clk.






1. dont set mco ! master clk out - this will need much higher clk 

2. why not use SAI ? (i use it , seems better working than spi/i2s, at least with 32bit data)







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1. I can't not generate MLCK. Unfortunately, this is not the solution. MCLK must be generated by STM for external DAC. Moreover (according to RM0481) no higher frequency than 12.288 MHz is needed to generate MCLK (using the other parameters I mentioned earlier). The condition is to set I2SDIV to 0, which is theoretically possible, but in practice CubeMX does not allow it.


2. There is no reason, I guess I'll have to use SAI. When I configured SAI with these settings, I didn't notice any such problems. We'll see if it actually works.

Chief II

For I2S generally SAI is a much more flexible peripheral and should be the first choice.