STM32 MCUs Products

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Resolved! External SRAM issue

Hello,I hope someone can help with this riddle.We just started working with our custom board, based on stm32h743 (untill now we worked with eval stm32h743-eval board).The internal memories, GPIOs and other interfaces works OK, but we have the followi...

ranran by Senior II
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Sector Erasing in STM32--chip crashes on 256kB erase

I am working on erasing sectors sequentially in my MCU, from Sector 2 through Sector 7 (the size of flash where my firmware will live). I have found that sequential sector erases will occasionally fail, and any attempt to erase a sector of size 256k...

rsoc by Associate III
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NAND Flash File system

I am working on raw NAND Flash memory with STM32L496 DISCOVERY board, and want implement file system which should include wear-leveling and bad block handling without any operating system .which file system should i use???is there any porting documen...

aahme.4 by Associate II
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Resolved! get interrupt state

How to get interrupt state (enabled or disabled) via HAL?In my void I need to do HAL_TIM_OC_Stop_IT() only if this interrupt enabled.

NVIC_SCBDeInit is in contraddiction with Cortex manual (??)

At the end of NVIC_SCBDeInit I see these instructions:[...]SCB->CFSR = 0xFFFFFFFF;SCB->HFSR = 0xFFFFFFFF;SCB->DFSR = 0xFFFFFFFF;The first one is a status register. Why writing it?For the second one the manual states:"This register is read, write to c...

sirpak by Associate II
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Resolved! Where and how are some SYSCFG registers stored?

Hello,I read ref manual part about SYSCFG (STM32H7 in my case). There are some regs that have an undefined reset value and the meaning of the regs is so that the contents is important at HW reset (BOOT_ADDx, BANK_SWAP). These regs are marked read onl...