About Danish1

Danish1 · 2024-01-22

I have been using microSD chips reliably for many years with stm32f4, stm32h7 and stm32l4.But for one of my products, where space is at a premium, I am trying to use a SD-NAND chip XTSD04G, and I am running into occasional errors where an SDIO R1 com...

Danish1 · 2021-12-20

Does anyone have any experience of trying to control non-exisistant pins?I have a design that takes stm32f767 in the lqfp100 package. But none seem to be available.Looking around, I managed to procure a small run of stm32f779* in the wlcsp180 package...

Danish1 · 2021-01-27

I have a stm32f427 with 1Mx16 external SRAM and SDMMC.I am reading the SDMMC by DMA into the SRAM in two blocks of 512 bytes into a 1024 byte buffer.The SRAM is mapped from 0x64000000 - 0x641fffff. Address and data are not multiplexedI have now disco...

Danish1 · 2019-09-18

I am looking into the possibility of using a stm32 microcontroller (probably stm32f030) to directly* control the power transistors in a switch-mode power supply, in order to generate a high-power waveform.My current thinking has a PMOS switch transis...

Danish1 · 2019-05-13

I am in the process of porting some code from stm32F405 to stm32L496 in the hope of reducing current consumption.One of the things my code does is write to an SD card, and because it writes a lot of data, I useSD_CMD_WRITE_MULT_BLOCKAnd then repeat {...

Danish1 · 2024-11-19

I conclude you are not using LSE. That is the slowest to start in my experience.As to the order of doing things, you could start the PLL before setting the APB/AHB dividers and wait-states. Only then wait for PLL loch. That way some of the PLL startu...

Danish1 · 2024-11-18

You are right - the cpu can be doing other things while waiting for e.g. the pll to stabilise. But stm32cube is meant to be simple, and code that takes advantage of this otherwise-wasted cpu time gets complicated.For example the pll might overshoot t...

Danish1 · 2024-10-24

Also study the DMA chapter of the Reference Manual for your stm32.I know this is a long and complicated document and it takes effort to understand, but that just reflects the fact that stm32 are extremely powerful devices.

Danish1 · 2024-10-21

Are you clear on what ST mean by 10% to 90%? 10% to 90% of what?Looking at the graph, it seems clear to me that 0% is Vhsel (i.e. 0.3 of Vdd, so around 1V) and 100% is Vhseh (0.7 of Vdd, so around 2.3V)So ST are saying the waveform has to go from bel...

Danish1 · 2024-10-21

you mean I can, reprogram GPIO to change SPI pins to manage what I want to do, just I have a question, is it possible I just remap MISO pin and rest pins remain as before?Yes you can by updating the GPIOx->MODER as appropriate. The only caveat is t...

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SDIO Error when use SD NAND chip

How are non-existent pins / ports wired up

DMA to external SRAM misses bytes part-way through transfer

pwm with asymmetric dead-time

stm32l496 SDMMC Correct Sequence for writing multiple blocks

Re: Wait for HSI/PLL/Sysclk etc etc ready - Why???

Re: Wait for HSI/PLL/Sysclk etc etc ready - Why???

Re: How do I set up DMA to circular mode on STM32H5 without HAL

Re: Why is the high level range 0.7VDD~VDD and the low level range 0.3VDD~VSS in Table 21 ,while the rise time in Figure 19 ranges from 10% to 9

Re: Serial SPI in one slave