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Hello.I'm using STM32L151C8T6 for some simple task. In the beginning I used MSI clock and everything was fine. But I decided to switch to HSI and now I got problems using USART1, namely I think that the USART1 periphery isn't properly initialized due...
Hello ,I want to configure a timer which start and runs for specific duration and stops automaticallyand when again i want to start that timer i could be able to start timer and agian stops automaticallyduration is fixed all timeDipak Garasiya
i want to implement a timer which make a perticular pin to toggle at perticular time duration the duration could I set manaully.
Hi,my question is simple , i have these parameter :Can_Clock = 48 MHz Prescaler = 1;NominalTimeSeg1 = 18NominalTimeSeg2 = 4and this is the MX_FDCAN1_Init() :static void MX_FDCAN1_Init(void) { /* USER CODE BEGIN FDCAN1_Init 0 */ /* USER CODE E...
Posted on January 16, 2018 at 10:34Hello,I need to control the acquisition and generation of a signal using the STM32F746ZG and its internal DAC and ADC. The idea is to trigger the DAC using one timer and the ADC using another timer (without the use...
I got a sample cubemx project which is in STM32f4 series using FREERTOS, my hardware is designed for STM32F0 so i cant use the sample code.so please suggest a method..
I ported openocd to the stm32l522. https://github.com/morbos/openocd-0.10.1openocd -f board/st_nucleo_l522.cfgFrom there you can remote connect from gdb, flash, and see the s/ns processor regs. Watchpoints work also.Hedley
Hello,On my custom designed PCB, there is a STM32F7 processor. With SPI DMA interface, I try to get the converting values of the external ADC. But everytime I get 3.1V in debug session. So how can I read the correct values based on the input signal?w...
My board has QSPI NOR memory (MT25QL256, 32MB) and STM32H750. I used Studio, CubeMX and CubeProgrammer to work with QSPI external memory on F746G-Disco board with no problem. But I have problem on my board with QSPI. My H750-MT25QL schm is same as in...
Looking for confirmation that the SDRAM data bits can be swapped within their byte lanes (D15..D8, D7..D0) to reduce the routing complexity. We are using vanilla SDRAM (non-DDR), specifically the ISSI IS42S32800G.Thanks.
