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Resolved! How to configure PWM as Gated output?

Hi,I am using STM32F072VBT6. I need a PWM waveform output that is gated with a PWM output of another timer channel.I am using TIM3_CH1 as the master that will control the output of another PWM of TIM2_CH1. Please refer the image for clarity. I need w...

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the RM0090 reference manual for 2014 ,in the description of the “Chip Select togglest�? different from RM00990 reference manual for 2018,why?

the RM0090 reference manual for 2014 ,in the description of the “Chip Select togglest�? different from RM00990 reference manual for 2018,which one is correct?The results of our tests are consistent with reference manual for 2014,Is it wrong in RM0099...

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cxiao.6 by Associate II
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I have a question,when changed cpu from stmf407 to stm32f427 .sometimes, read a wrong data from extern sram access by FMC ,it's happend in most of the cases in interrupt ,someone have the same problem?

my English is poor,In the same program ,cpu 407 do not have this problem,only happened in 427​,somtimes.It's like 2.3.4 Corruption of data read from the FMC. in <Errata sheet - STM32F42xx and STM32F43xx - STM32F427/437 and STM32F429/439 line limitati...

cxiao.6 by Associate II
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printf function call causes hard fault

Hi all,I am working on a STM32F103VEtx MCU. In my firmware I have redirected the printf function to a UART for debugging purposes. When I start running the code, the printf function causes the hard fault handler to hit. Please see the call stack att...

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Effect of timer CCR not in range 0<CCR<ARR

DMA requests are still generated if the CCR is outside the auto-reload rangeThe DMA request is is generated when CNT reaches 0 rather than being disabled.Processor is a STM32H750is this a bug or a feature - it should be documented anyway

pbayton9 by Associate II
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