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WWDG reset failure In the Self Test library

KVija
Associate II

MCU : STM32H743ZTi

OS : RTEMS

STL: en.x-cube-classb-v2-3-0

STL code integrated with RTEMS os plat form and STL test initiated from boot start area. WWDG test is working as expected until RTC and HAL_PWR_EnableBkUpAccess is disable.

After enabling the RTC and back access area, WWDG not firing the reset and code staying at tim7(hal tick time).

/**

 * @brief RTC Initialization Function

 * @param None

 * @retval None

 */

void MX_RTC_Init(void)

{

 /* USER CODE BEGIN RTC_Init 0 */

 /* USER CODE END RTC_Init 0 */

 RTC_TimeTypeDef sTime = {0};

 RTC_DateTypeDef sDate = {0};

 /* USER CODE BEGIN RTC_Init 1 */

 /* USER CODE END RTC_Init 1 */

 /** Initialize RTC Only 

 */

 hrtc.Instance = RTC;

 hrtc.Init.HourFormat = RTC_HOURFORMAT_24;

 hrtc.Init.AsynchPrediv = 127;

 hrtc.Init.SynchPrediv = 255;

 hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;

 hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;

 hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;

 hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;

 if (HAL_RTC_Init(&hrtc) != HAL_OK)

 {

  Error_Handler();

 }

 /* USER CODE BEGIN Check_RTC_BKUP */

 if(HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_DR0) != 0x32F2){

 /* USER CODE END Check_RTC_BKUP */

 /** Initialize RTC and set the Time and Date 

 */

 sTime.Hours = 0;

 sTime.Minutes = 0;

 sTime.Seconds = 0;

 sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;

 sTime.StoreOperation = RTC_STOREOPERATION_RESET;

 if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK)

 {

  Error_Handler();

 }

 sDate.WeekDay = RTC_WEEKDAY_MONDAY;

 sDate.Month = RTC_MONTH_JANUARY;

 sDate.Date = 1;

 sDate.Year = 0;

 if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK)

 {

  Error_Handler();

 }

 /** Enable the TimeStamp 

 */

 if (HAL_RTCEx_SetTimeStamp(&hrtc, RTC_TIMESTAMPEDGE_RISING, RTC_TIMESTAMPPIN_DEFAULT) != HAL_OK)

 {

  Error_Handler();

 }

 /* USER CODE BEGIN RTC_Init 2 */

 HAL_RTCEx_BKUPWrite(&hrtc,RTC_BKP_DR0,0x32F2);

 }

 /* USER CODE END RTC_Init 2 */

}

/******************************************************************************/

/**

 * @brief write the test result into the backup register

 *

 * @param : testResult

 *  

 * @retval : None

 */

void stlBackupRegWrite(uint32_t testResult)

{

  __HAL_RTC_WRITEPROTECTION_DISABLE(&hrtc);

  HAL_PWR_EnableBkUpAccess();

  

  HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_DR0, testResult);

  

  //__HAL_RTC_WRITEPROTECTION_ENABLE(&hrtc);

  

  if (testResult != stlBackupRegRead() )

  {

#if defined(STL_VERBOSE) || defined(STL_VERBOSE_POR)

   stlPrintf("backup write failed!");

#endif

  }

  HAL_PWR_DisableBkUpAccess();

}

/******************************************************************************/

/**

 * @brief read the test result from backup register

 *

 * @param : void

 *  

 * @retval : test result

 */

uint32_t stlBackupRegRead(void)

{

  uint32_t readData;

  

  HAL_PWR_EnableBkUpAccess();

  readData = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_DR1);

  HAL_PWR_DisableBkUpAccess();

  return readData;

}

Is there any relation between WWDG and Backup access ?

Please let me know any finds. For our application we need to store STL test result in the backup register.

3 REPLIES 3
TDK
Guru

So you're saying the WWDG stops working, even though it was activated? Seems unlikely. Does WWDG_CR reflect being on (WDGA=1) and does the counter stop decrementing?

Backup domain and WWDG should be independent.

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KVija
Associate II

Thanks for your input. Yes it's independent.

It seems like WWDG trigger reset, but after the reset system tick timer (tim7 ) getting capture interrupt and code looping in the interrupt. Please look the following attachments.

0693W000001piRlQAI.png0693W000001piRNQAY.png

KVija
Associate II

Please find the screenshot of the debugging information. After WWDG reset,TIM7CH2 interrupt is getting triggered until hard reset. After reset, TIM7CH2 interrupt is not triggering and application runs as expected.

I don't have a clue that why systick timer (TIM7 ) getting capture interrupt on WWDG reset.