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STM32G4 devices are split into 2 flash categories per the datasheet: Category 2 devices (STM32G43x/G44x) which have only single-bank capable flash with a capacity up to 128kB and Category 3 devices which are dual-bank capable and have up to 512kB of ...
I have tried to generate STM32H747I-DISCO's GPIO code.After loading flash, it can be executed normally.But after power on the MCU, the code can't be executed and the MCU can't be target with ST-link.I must pull-up boot0 and erase flash before I can r...
When I debug in serial wire mode, can I use the NJTRST pin as a reset pin?Because I do n’t want to lead the chip NRST pin.
Hi all!I'm trying to measure a PWM frequency signal using the input capture channel 1 of TIM3, but it won't work.i'm using NUCLEO F446RE board, here is my code:#include "stm32f4xx.h" // Device header#include "lcd_H.h"int main(void){uint16_t capt1 = 0...
Hello,in AN4539, the HRTIM cookbook, on page 56 C.3, the application note AN5094 "Migrating between STM32F334/303 lines and STM32G474xx/G431xxis" is mentioned. Unfortunately, i cannot find this document. Any suggestions?Kind regards,Greg
RM0440 states in 46.8.3 that SW-DP ID code is 0x1BA01477. However, it's actually 0x2BA01477.
RM0440 Rev 3 (last version) recomend to set 4WS for 170MHz CPU clockRM0440 Rev 2 recomend to set 8WS for 170MHz CPU clockST driver library (STM32G4xx_HAL_Driver) function LL_PLL_ConfigSystemClock_HSE() set 8WS for 170Mhz clock. Which Flash WS setting...
STM32G4 CPU speed. I am migrating a project from the STM32F405RG to the STM32G473RE. System clock frequency for both is 168MHz. I have found the code runs at about half speed on the STM32G473 and I would like to know why and how to fix it.The STM32G4...
Hello,I'm working on a project involving the STM32L471 device clocked at 80Mhz (Externalcrystal oscillator with internal PLL).We are using ADC1, also clocked at 80Mhz (CKMODE = 0x01)We are noticing an issue concerning the calibration (and the consequ...
Hi, I am trying to get working IWDG using HAL_IWDG library and I am not able to refresh the watchdog before IWDG_Reset. As is said in page 6: (https://www.st.com/content/ccc/resource/training/technical/product_training/group0/01/24/22/29/38/70/40/57/...
