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I have some data that is accessed from a normal context and also from an IRQ. I am disabling the interrupt to prevent interrupted access. So no concerns there. However, what about forcing both the normal context and the interrupt context to have the ...
HiWe are facing problems when reading a data that is written to the flash using the following function?Every time we write in reading the data the micro-controller crashes. Even if I want to see the content of the flash in that particular address usi...
I have a custom PCB with a STM32H7A3ZI MCU, and a S27KL0642S27KS0642 Hyperbus RAM.My code, as well as the app note (AN5050) I'm following sets up the RAM for memory mapped access.I've checked and rechecked the pinout and configuration, but every time...
The memory I'm writing is 16-byte aligned (both flash destination and RAM source) and a multiple of 16 bytes in length. Using HAL to write the flash. Writing the first quadword fails with the error OPTWERR. This is quite unexpected since I am not, as...
I have an application running on STM32G491 which uses the RTC. There is an external 32768Hz crystal and a backup coin cell battery (I have checked that it is not depleted: 3.12V). There are two issues:Scenario #1: I pull the main battery, wait a bit,...
Other chips have the erratum "Transmit data FIFO is corrupted when a write sequence to the FIFO is interrupted with accesses to certain OTG_HS registers" (eg ES0392 2.25.2 for STM32H743). It isn't listed in the ES0596 rev5 errata for STM32H7Rxx/7Sxx ...
Hello ST support,As a customer working on a project using STM32, I am looking for STM32 development or evaluation boards that feature a socket-based MCU instead of a soldered one. This allows for easy replacement of the microcontroller during the use...
I'm using STM32F070CBT at 8mhz with almost all pins active (used for GPIOs, PWM, SPI,I2C,etc) , i'm using a timer to enter stop mode with low power regulator and waking up using GPIO external event, after waking up i checked that PWMs and GPIOs are s...
I want to capture images larger than 0xFFFF via DCMI using double buffering with two GPDMA1 linked list nodes. As guidance, I'm following the DCMI_ContinuousCap_EmbeddedSynchMode example. However, it seems that the DCMI_DMAXferCplt function is writte...
Over in the post https://community.st.com/t5/stm32-mcus-embedded-software/stm32u5-fracn-not-working/m-p/691980 an issue was raised with the delay necessary to ensure live updates of the FRAC N PLL register. The reference manual for the STM32U5 has be...
