STM32F746G-DISCO, FLASH, read
HiHow to read in STM32F746G-DISCO FLASH for a specific address?
Ask questions, find answers, and share insights on STM32 products and their technical features.
HiHow to read in STM32F746G-DISCO FLASH for a specific address?
Hi, I am new to this STM. I am working on a touch sensor project. I need to use 4 touch buttons. I am having an STM32F051R8Tx board. how to read those touch buttons. Please help me.
32.768KHz的�?起振,�?�尔会有32K的频率,这个晶振主�?是给内部的RTC使用的,负载电容�?�大�?�?��?都试了�?行。
Hi,Hope everybody is doing great !I am trying to have quectel M66 2G modem running along with our application running on L476RG. I found the celluar package from ST for B96 modem and could integrate it to our application and it has all the features w...
Hi,I am having problems measuring accurate temperatures with the internal temperature sensor of the STM32L011D4P7 over the full device temperature range of -40 °C to 130 °C.What I did: Measuring the temperature as described in the Reference Manual (R...
Hello,So I want to add RFU or OTA to my code as a feature. I saw an rfu source code to one of the expansion of STM32, however it is disabled. I tried to enable it by defining RFU but somehow there are missing files such as se_def.h and se_interface.h...
Hi, I am new to this STM32 development. I am using STM32F051R8Tx board and STM32CubeIDE. I want to read the push button for long press and short press how to do this?
Hello community,I am trying to write time critical code which involves an STM32f412ZG Nucleo 144 board and a RPi communicating over SPI protocol. I have an IMU sensor communicating to STM32 board via I2C interface. I have 3 tasks, which function as ...
I am working on STM32H7 (Cortex-M7) and using IWDG for monitoring. I am wondering if there is a way to record Cortex-M7 CPU registers (General Purpose (Rx), SP, LR and PC) when IWDG runs out. Either before or after the reset.I understand the RCC regi...
Hi,I am working on interfacing IS25LP128 128Mbit QSPI Flash with STM32H743 Nucleo board. I am running into problem with how the QSPI controller is driving the NCS line. The flash requires that the chip select remains low between command and data read...